1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.FuType 29import freechips.rocketchip.diplomacy.BufferParams 30 31class MBufferBundle(implicit p: Parameters) extends VLSUBundle{ 32 val data = UInt(VLEN.W) 33 val mask = UInt(VLENB.W) 34 val flowNum = UInt(flowIdxBits.W) 35 val exceptionVec = ExceptionVec() 36 val uop = new DynInst 37 // val vdOffset = UInt(vOffsetBits.W) 38 val sourceType = VSFQFeedbackType() 39 val flushState = Bool() 40 val vdIdx = UInt(3.W) 41 // for exception 42 val vstart = UInt(elemIdxBits.W) 43 val vl = UInt(elemIdxBits.W) 44 val vaddr = UInt(VAddrBits.W) 45 val fof = Bool() 46 val vlmax = UInt(elemIdxBits.W) 47 48 def allReady(): Bool = (flowNum === 0.U) 49} 50 51abstract class BaseVMergeBuffer(isVStore: Boolean=false)(implicit p: Parameters) extends VLSUModule{ 52 val io = IO(new VMergeBufferIO(isVStore)) 53 54 def EnqConnect(source: MergeBufferReq): MBufferBundle = { 55 val sink = WireInit(0.U.asTypeOf(new MBufferBundle)) 56 sink.data := source.data 57 sink.mask := source.mask 58 sink.flowNum := source.flowNum 59 sink.exceptionVec := 0.U.asTypeOf(ExceptionVec()) 60 sink.uop := source.uop 61 sink.sourceType := 0.U.asTypeOf(VSFQFeedbackType()) 62 sink.flushState := false.B 63 sink.vdIdx := source.vdIdx 64 sink.fof := source.fof 65 sink.vlmax := source.vlmax 66 sink.vl := source.uop.vpu.vl 67 sink.vstart := 0.U 68 sink 69 // sink.vdOffset := source.vdOffset 70 } 71 def DeqConnect(source: MBufferBundle): MemExuOutput = { 72 val sink = WireInit(0.U.asTypeOf(new MemExuOutput(isVector = true))) 73 sink.data := source.data 74 sink.mask.get := source.mask 75 sink.uop.exceptionVec := source.exceptionVec 76 sink.uop := source.uop 77 sink.uop.vpu.vmask := source.mask 78 sink.debug := 0.U.asTypeOf(new DebugBundle) 79 sink.vdIdxInField.get := 0.U 80 sink.vdIdx.get := source.vdIdx 81 sink.uop.vpu.vstart := source.vstart 82 sink.uop.vpu.vl := source.vl 83 sink 84 } 85 def ToLsqConnect(source: MBufferBundle): FeedbackToLsqIO = { 86 val sink = WireInit(0.U.asTypeOf(new FeedbackToLsqIO)) 87 val hasExp = source.uop.exceptionVec.asUInt.orR 88 sink.robidx := source.uop.robIdx 89 sink.uopidx := source.uop.uopIdx 90 sink.feedback(VecFeedbacks.COMMIT) := !hasExp 91 sink.feedback(VecFeedbacks.FLUSH) := hasExp 92 sink.feedback(VecFeedbacks.LAST) := true.B 93 sink.vstart := source.vstart // TODO: if lsq need vl for fof? 94 sink.vaddr := source.vaddr 95 sink.vl := source.vl 96 sink 97 } 98 // freeliset: store valid entries index. 99 // +---+---+--------------+-----+-----+ 100 // | 0 | 1 | ...... | n-2 | n-1 | 101 // +---+---+--------------+-----+-----+ 102 val freeList: FreeList 103 val uopSize: Int 104 val enqWidth = io.fromSplit.length 105 val deqWidth = io.uopWriteback.length 106 val pipeWidth = io.fromPipeline.length 107 108 val entries = Reg(Vec(uopSize, new MBufferBundle)) 109 val needCancel = WireInit(VecInit(Seq.fill(uopSize)(false.B))) 110 val allocated = RegInit(VecInit(Seq.fill(uopSize)(false.B))) 111 val freeMaskVec = WireInit(VecInit(Seq.fill(uopSize)(false.B))) 112 val uopFinish = RegInit(VecInit(Seq.fill(uopSize)(false.B))) 113 val needRSReplay = RegInit(VecInit(Seq.fill(uopSize)(false.B))) 114 // enq, from splitPipeline 115 // val allowEnqueue = 116 val cancelEnq = io.fromSplit.map(_.req.bits.uop.robIdx.needFlush(io.redirect)) 117 val canEnqueue = io.fromSplit.map(_.req.valid) 118 val needEnqueue = (0 until enqWidth).map{i => 119 canEnqueue(i) && !cancelEnq(i) 120 } 121 122 for ((enq, i) <- io.fromSplit.zipWithIndex){ 123 freeList.io.doAllocate(i) := false.B 124 125 freeList.io.allocateReq(i) := true.B 126 127 val offset = PopCount(needEnqueue.take(i)) 128 val canAccept = freeList.io.canAllocate(offset) 129 val enqIndex = freeList.io.allocateSlot(offset) 130 enq.req.ready := canAccept 131 132 when(needEnqueue(i) && enq.req.ready){ 133 freeList.io.doAllocate(i) := true.B 134 // enqueue 135 allocated(enqIndex) := true.B 136 uopFinish(enqIndex) := false.B 137 needRSReplay(enqIndex) := false.B 138 139 entries(enqIndex) := EnqConnect(enq.req.bits)// initial entry 140 } 141 142 enq.resp.bits.mBIndex := enqIndex 143 enq.resp.bits.fail := false.B 144 enq.resp.valid := canAccept //resp in 1 cycle 145 } 146 147 //redirect 148 for (i <- 0 until uopSize){ 149 needCancel(i) := entries(i).uop.robIdx.needFlush(io.redirect) && allocated(i) 150 when (needCancel(i)) { 151 allocated(i) := false.B 152 freeMaskVec(i) := true.B 153 uopFinish(i) := false.B 154 needRSReplay(i):= false.B 155 } 156 } 157 freeList.io.free := freeMaskVec.asUInt 158 //pipelineWriteback 159 // handle the situation where multiple ports are going to write the same uop queue entry 160 val mergePortMatrix = Wire(Vec(pipeWidth, Vec(pipeWidth, Bool()))) 161 val mergedByPrevPortVec = Wire(Vec(pipeWidth, Bool())) 162 (0 until pipeWidth).map{case i => (0 until pipeWidth).map{case j => 163 mergePortMatrix(i)(j) := (j == i).B || 164 (j > i).B && 165 io.fromPipeline(j).bits.mBIndex === io.fromPipeline(i).bits.mBIndex && 166 io.fromPipeline(j).valid 167 }} 168 (0 until pipeWidth).map{case i => 169 mergedByPrevPortVec(i) := (i != 0).B && Cat((0 until i).map(j => 170 io.fromPipeline(j).bits.mBIndex === io.fromPipeline(i).bits.mBIndex && 171 io.fromPipeline(j).valid)).orR 172 } 173 dontTouch(mergePortMatrix) 174 dontTouch(mergedByPrevPortVec) 175 176 // for exception, select exception, when multi port writeback exception, we need select oldest one 177 def selectOldest[T <: VecPipelineFeedbackIO](valid: Seq[Bool], bits: Seq[T], sel: Seq[UInt]): (Seq[Bool], Seq[T], Seq[UInt]) = { 178 assert(valid.length == bits.length) 179 assert(valid.length == sel.length) 180 if (valid.length == 0 || valid.length == 1) { 181 (valid, bits, sel) 182 } else if (valid.length == 2) { 183 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 184 for (i <- res.indices) { 185 res(i).valid := valid(i) 186 res(i).bits := bits(i) 187 } 188 val oldest = Mux(valid(0) && valid(1), 189 Mux(sel(0) < sel(1), 190 res(0), res(1)), 191 Mux(valid(0) && !valid(1), res(0), res(1))) 192 (Seq(oldest.valid), Seq(oldest.bits), Seq(0.U)) 193 } else { 194 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2), sel.take(sel.length / 2)) 195 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2)), sel.takeRight(sel.length - (sel.length / 2))) 196 selectOldest(left._1 ++ right._1, left._2 ++ right._2, left._3 ++ right._3) 197 } 198 } 199 200 val pipeValid = io.fromPipeline.map(_.valid) 201 val pipeBits = io.fromPipeline.map(x => x.bits) 202 val wbElemIdx = pipeBits.map(_.elemIdx) 203 val wbMbIndex = pipeBits.map(_.mBIndex) 204 val wbElemIdxInField = wbElemIdx.zip(wbMbIndex).map(x => x._1 & (entries(x._2).vlmax - 1.U)) 205 206 val hasExcp = pipeBits.zip(mergePortMatrix).map{case (port, v) => 207 val thisPortExcp = port.exceptionVec.asUInt.orR && port.mask.orR 208 val mergePortExcp = (0 until pipeWidth).map{case i => 209 (v(i) && io.fromPipeline(i).bits.exceptionVec.asUInt.orR && io.fromPipeline(i).bits.mask.orR) // this port have exception or merged port have exception 210 }.reduce(_ || _) 211 thisPortExcp || mergePortExcp 212 } 213 214 for((pipewb, i) <- io.fromPipeline.zipWithIndex){ 215 val (_, selPort, _) = selectOldest(mergePortMatrix(i), pipeBits, wbElemIdxInField) 216 val selElemInfield = selPort.head.elemIdx & (entries(wbMbIndex(i)).vlmax - 1.U) 217 val selExceptionVec = selPort.head.exceptionVec 218 219 when((entries(wbMbIndex(i)).vstart > selElemInfield) && hasExcp(i) && pipewb.valid){ 220 when(!entries(wbMbIndex(i)).fof || selElemInfield === 0.U){ 221 // For fof loads, if element 0 raises an exception, vl is not modified, and the trap is taken. 222 entries(wbMbIndex(i)).vstart := selElemInfield 223 entries(wbMbIndex(i)).exceptionVec := selExceptionVec 224 }.otherwise{ 225 entries(wbMbIndex(i)).vl := selElemInfield 226 } 227 } 228 } 229 230 // for pipeline writeback 231 for((pipewb, i) <- io.fromPipeline.zipWithIndex){ 232 val wbIndex = pipewb.bits.mBIndex 233 val flowNumOffset = Mux(pipewb.bits.usSecondInv, 234 2.U, 235 PopCount(mergePortMatrix(i))) 236 val sourceTypeNext = entries(wbIndex).sourceType | pipewb.bits.sourceType 237 val hasExp = pipewb.bits.exceptionVec.asUInt.orR 238 239 // if is VLoad, need latch 1 cycle to merge data. only flowNum and wbIndex need to latch 240 val latchWbValid = if(isVStore) pipewb.valid else RegNext(pipewb.valid) 241 val latchWbIndex = if(isVStore) wbIndex else RegEnable(wbIndex, pipewb.valid) 242 val latchFlowNum = if(isVStore) flowNumOffset else RegEnable(flowNumOffset, pipewb.valid) 243 val latchMergeByPre = if(isVStore) mergedByPrevPortVec(i) else RegEnable(mergedByPrevPortVec(i), pipewb.valid) 244 when(latchWbValid && !latchMergeByPre){ 245 entries(latchWbIndex).flowNum := entries(latchWbIndex).flowNum - latchFlowNum 246 } 247 248 when(pipewb.valid){ 249 entries(wbIndex).sourceType := sourceTypeNext 250 entries(wbIndex).flushState := pipewb.bits.flushState 251 } 252 when(pipewb.valid && !pipewb.bits.hit){ 253 needRSReplay(wbIndex) := true.B 254 } 255 pipewb.ready := true.B 256 XSError((entries(latchWbIndex).flowNum - latchFlowNum > entries(latchWbIndex).flowNum) && latchWbValid && !latchMergeByPre, "FlowWriteback overflow!!\n") 257 XSError(!allocated(latchWbIndex) && latchWbValid, "Writeback error flow!!\n") 258 } 259 // for inorder mem asscess 260 io.toSplit := DontCare 261 262 //uopwriteback(deq) 263 for (i <- 0 until uopSize){ 264 when(allocated(i) && entries(i).allReady()){ 265 uopFinish(i) := true.B 266 } 267 } 268 val selPolicy = SelectOne("circ", uopFinish, deqWidth) // select one entry to deq 269 for(((port, lsqport), i) <- (io.uopWriteback zip io.toLsq).zipWithIndex){ 270 val canGo = port.ready 271 val (selValid, selOHVec) = selPolicy.getNthOH(i + 1) 272 val entryIdx = OHToUInt(selOHVec) 273 val selEntry = entries(entryIdx) 274 val selFire = selValid && canGo 275 when(selFire){ 276 freeMaskVec(entryIdx) := true.B 277 allocated(entryIdx) := false.B 278 uopFinish(entryIdx) := false.B 279 needRSReplay(entryIdx):= false.B 280 } 281 //writeback connect 282 port.valid := selFire && allocated(entryIdx) && !needRSReplay(entryIdx) 283 port.bits := DeqConnect(selEntry) 284 //to lsq 285 lsqport.bits := ToLsqConnect(selEntry) // when uopwriteback, free MBuffer entry, write to lsq 286 lsqport.valid:= selFire && allocated(entryIdx) && !needRSReplay(entryIdx) 287 //to RS 288 io.feedback(i).valid := selFire && allocated(entryIdx) 289 io.feedback(i).bits.hit := !needRSReplay(entryIdx) 290 io.feedback(i).bits.robIdx := selEntry.uop.robIdx 291 io.feedback(i).bits.sourceType := selEntry.sourceType 292 io.feedback(i).bits.flushState := selEntry.flushState 293 io.feedback(i).bits.dataInvalidSqIdx := DontCare 294 io.feedback(i).bits.uopIdx.get := selEntry.uop.uopIdx 295 } 296 297 QueuePerf(uopSize, freeList.io.validCount, freeList.io.validCount === 0.U) 298} 299 300class VLMergeBufferImp(implicit p: Parameters) extends BaseVMergeBuffer(isVStore=false){ 301 override lazy val uopSize = VlMergeBufferSize 302 println(s"VLMergeBuffer Size: ${VlMergeBufferSize}") 303 override lazy val freeList = Module(new FreeList( 304 size = uopSize, 305 allocWidth = VecLoadPipelineWidth, 306 freeWidth = deqWidth, 307 enablePreAlloc = false, 308 moduleName = "VLoad MergeBuffer freelist" 309 )) 310 311 //merge data 312 val flowWbElemIdx = Wire(Vec(LoadPipelineWidth, UInt(elemIdxBits.W))) 313 val flowWbElemIdxInVd = Wire(Vec(LoadPipelineWidth, UInt(elemIdxBits.W))) 314 315 for((pipewb, i) <- io.fromPipeline.zipWithIndex){ 316 /** step0 **/ 317 val wbIndex = pipewb.bits.mBIndex 318 val alignedType = pipewb.bits.alignedType 319 val elemIdxInsideVd = pipewb.bits.elemIdxInsideVd 320 flowWbElemIdx(i) := pipewb.bits.elemIdx 321 flowWbElemIdxInVd(i) := elemIdxInsideVd.get 322 323 val mergedData = mergeDataWithElemIdx( 324 oldData = entries(wbIndex).data, 325 newData = io.fromPipeline.map(_.bits.vecdata.get), 326 alignedType = alignedType(1,0), 327 elemIdx = flowWbElemIdxInVd, 328 valids = mergePortMatrix(i) 329 ) 330 /* this only for unit-stride load data merge 331 * cycle0: broden 128-bits to 256-bits (max 6 to 1) 332 * cycle1: select 128-bits data from 256-bits (16 to 1) 333 */ 334 val (brodenMergeData, brodenMergeMask) = mergeDataByIndex( 335 data = io.fromPipeline.map(_.bits.vecdata.get).drop(i), 336 mask = io.fromPipeline.map(_.bits.mask).drop(i), 337 index = io.fromPipeline(i).bits.elemIdxInsideVd.get, 338 valids = mergePortMatrix(i).drop(i) 339 ) 340 /** step1 **/ 341 val pipewbValidReg = RegNext(pipewb.valid) 342 val wbIndexReg = RegEnable(wbIndex, pipewb.valid) 343 val mergeDataReg = RegEnable(mergedData, pipewb.valid) // for not Unit-stride 344 val brodenMergeDataReg = RegEnable(brodenMergeData, pipewb.valid) // only for Unit-stride 345 val brodenMergeMaskReg = RegEnable(brodenMergeMask, pipewb.valid) 346 val mergedByPrevPortReg = RegEnable(mergedByPrevPortVec(i), pipewb.valid) 347 val regOffsetReg = RegEnable(pipewb.bits.reg_offset.get, pipewb.valid) // only for Unit-stride 348 val isusMerge = RegEnable(alignedType(2), pipewb.valid) 349 350 val usSelData = Mux1H(UIntToOH(regOffsetReg), (0 until VLENB).map{case i => getNoAlignedSlice(brodenMergeDataReg, i, 128)}) 351 val usSelMask = Mux1H(UIntToOH(regOffsetReg), (0 until VLENB).map{case i => brodenMergeMaskReg(16 + i - 1, i)}) 352 val usMergeData = mergeDataByByte(entries(wbIndexReg).data, usSelData, usSelMask) 353 when(pipewbValidReg && !mergedByPrevPortReg){ 354 entries(wbIndexReg).data := Mux(isusMerge, usMergeData, mergeDataReg) // if aligned(2) == 1, is Unit-Stride inst 355 } 356 } 357} 358 359class VSMergeBufferImp(implicit p: Parameters) extends BaseVMergeBuffer(isVStore=true){ 360 override lazy val uopSize = VsMergeBufferSize 361 println(s"VSMergeBuffer Size: ${VsMergeBufferSize}") 362 override lazy val freeList = Module(new FreeList( 363 size = uopSize, 364 allocWidth = VecStorePipelineWidth, 365 freeWidth = deqWidth, 366 enablePreAlloc = false, 367 moduleName = "VStore MergeBuffer freelist" 368 )) 369 override def DeqConnect(source: MBufferBundle): MemExuOutput = { 370 val sink = Wire(new MemExuOutput(isVector = true)) 371 sink.data := DontCare 372 sink.mask.get := DontCare 373 sink.uop.exceptionVec := source.exceptionVec 374 sink.uop := source.uop 375 sink.debug := 0.U.asTypeOf(new DebugBundle) 376 sink.vdIdxInField.get := DontCare 377 sink.vdIdx.get := DontCare 378 sink.uop.vpu.vstart := source.vstart 379 sink 380 } 381} 382