style(Bundles): move bundles to Bundles.scala (#4247)

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic to the previous cycle.

---

**Timing issue caused by long exception logic of load writeback to
`VLMergeBuffer`:**
- Add one cycle to the load writeback exception, now the same number of
cycles as the load write back data.

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fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks that
triggered the exception and pick the oldest.

But amazingly, I just realised that the implementation doesn't match the
annotation. The current implementation can be problematic in that if
the write-back port that did not have an exception is older, the port that
triggered the exception is not elected.

Use s3_exception to try to optimise timing.

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fix(VLSU): `mergebuffer` threshold was added (#4103)

To solve the stuckness caused by insufficient RAW, we use `threshold` to
control the execution of vector instructions.
When the mergebuffer has f

fix(VLSU): `mergebuffer` threshold was added (#4103)

To solve the stuckness caused by insufficient RAW, we use `threshold` to
control the execution of vector instructions.
When the mergebuffer has few free entries than it can hold in the flow,
we backpressure to make `IssueQueue` send the oldest `Uop` for us.

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fix(VSplit): inactive elements of `UnitStride` are no longer executed (#4100)

Now, we no longer have `inActive` is `unit-stride` sent to the pipeline.
This will fix some bugs caused by `inActive` no

fix(VSplit): inactive elements of `UnitStride` are no longer executed (#4100)

Now, we no longer have `inActive` is `unit-stride` sent to the pipeline.
This will fix some bugs caused by `inActive` not being handled properly in `LSU`.
And will theoretically result in some performance gains.

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feat(Zicclsm): refactoring misalign and support vector misalign

fix(VMergeBuffer): `uopFinish` should not be set when redirect (#3924)

If `uopFinish` is set when redirecting, it may cause incorrect dequeuing
and enqueuing conflicts, which may cause `allocated`

fix(VMergeBuffer): `uopFinish` should not be set when redirect (#3924)

If `uopFinish` is set when redirecting, it may cause incorrect dequeuing
and enqueuing conflicts, which may cause `allocated` to be unable to be
set correctly.

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refactor(MemBlock): turn on `dontTouch` only when debugging (#3792)

This will result in the delivery of clean generated code and may remove
some of the pseudo-paths.

fix(VMergeBuffer): vl of fof only allows setting smaller values (#3733)

The current condition, when there are no exceptions in the entry and the
frompipe carries an exception, will go directly to t

fix(VMergeBuffer): vl of fof only allows setting smaller values (#3733)

The current condition, when there are no exceptions in the entry and the
frompipe carries an exception, will go directly to the next level of
determining whether it is a fof instruction. If it is a fof instruction
and a non-zero element triggers an exception, the value of vl is
modified directly.

The fof instruction is regarded as a unit-stride instruction. Therefore,
when a fof uop is split into two access operations and both of them
trigger an exception at the pipe, both of them will modify the vl value
of the same entry, which may result in a situation where a smaller vl
value is overwritten by a larger vl value.

Therefore, this modification makes a judgement when modifying the vl
value, and only allows to write the vl value which is smaller than the
current vl of the entry.

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fix(Backend, Mem): add `isFromLoadUnit` to avoid other units polluting RegCache (#3731)

fix(fof): always use tail undisturbed when vl updated by un-raised exception.

fix(VMergeBuffer): fix the oldest logic of 'frompipe'

The more granular LastFlow is used to ensure that the FLOW after the abnormal element is not written to the sbuffer. The vExceptionFlag can only

fix(VMergeBuffer): fix the oldest logic of 'frompipe'

The more granular LastFlow is used to ensure that the FLOW after the abnormal element is not written to the sbuffer. The vExceptionFlag can only be cleared when the last flow out of the team.

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fix(VLSU): new vstart calculation method is adopted

feat(rv64v): support first only fault instruction

feat(VLSU): element in which the exception occurs needs to retain its old value

feat(VLSU): set vstart when the support vector accesses anomalies

feat(Trigger): add vector memory access Trigger logic

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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fix(exception): connect new address port for vector access exceptions (#3626)

The vector exception address comes from the VMergebuffer, which needs to
store all 64 bits addresses and connect to the

fix(exception): connect new address port for vector access exceptions (#3626)

The vector exception address comes from the VMergebuffer, which needs to
store all 64 bits addresses and connect to the LSQ exception processing.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

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timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

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VLSU: Fix exception generate of vector load/store (#3206)

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

VMergeBuffer: add ExceptionVec select By fuCfg for better timing and area