1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 72 // only unit-stride use lumop 73 // mop [1:0] 74 // 0 0 : unit-stride 75 // 0 1 : indexed-unordered 76 // 1 0 : strided 77 // 1 1 : indexed-ordered 78 // lumop[4:0] 79 // 0 0 0 0 0 : unit-stride load 80 // 0 1 0 0 0 : unit-stride, whole register load 81 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 82 // 1 0 0 0 0 : unit-stride fault-only-first 83 def vle = "b00_00_00000".U 84 def vlr = "b00_00_01000".U 85 def vlm = "b00_00_01011".U 86 def vleff = "b00_00_10000".U 87 def vluxe = "b00_01_00000".U 88 def vlse = "b00_10_00000".U 89 def vloxe = "b00_11_00000".U 90 91 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 92 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 93 } 94 95 object VstuType { 96 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 97 // only unit-stride use sumop 98 // mop [1:0] 99 // 0 0 : unit-stride 100 // 0 1 : indexed-unordered 101 // 1 0 : strided 102 // 1 1 : indexed-ordered 103 // sumop[4:0] 104 // 0 0 0 0 0 : unit-stride load 105 // 0 1 0 0 0 : unit-stride, whole register load 106 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 107 def vse = "b00_00_00000".U 108 def vsr = "b00_00_01000".U 109 def vsm = "b00_00_01011".U 110 def vsuxe = "b00_01_00000".U 111 def vsse = "b00_10_00000".U 112 def vsoxe = "b00_11_00000".U 113 114 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 115 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 116 } 117 118 object IF2VectorType { 119 // use last 2 bits for vsew 120 def iDup2Vec = "b1_00".U 121 def fDup2Vec = "b1_01".U 122 def immDup2Vec = "b1_10".U 123 def i2Vec = "b0_00".U 124 def f2Vec = "b0_01".U 125 def imm2Vec = "b0_10".U 126 def needDup(bits: UInt): Bool = bits(2) 127 def isImm(bits: UInt): Bool = bits(1) 128 } 129 130 object CommitType { 131 def NORMAL = "b000".U // int/fp 132 def BRANCH = "b001".U // branch 133 def LOAD = "b010".U // load 134 def STORE = "b011".U // store 135 136 def apply() = UInt(3.W) 137 def isFused(commitType: UInt): Bool = commitType(2) 138 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 139 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 140 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 141 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 142 } 143 144 object RedirectLevel { 145 def flushAfter = "b0".U 146 def flush = "b1".U 147 148 def apply() = UInt(1.W) 149 // def isUnconditional(level: UInt) = level(1) 150 def flushItself(level: UInt) = level(0) 151 // def isException(level: UInt) = level(1) && level(0) 152 } 153 154 object ExceptionVec { 155 val ExceptionVecSize = 16 156 def apply() = Vec(ExceptionVecSize, Bool()) 157 } 158 159 object PMAMode { 160 def R = "b1".U << 0 //readable 161 def W = "b1".U << 1 //writeable 162 def X = "b1".U << 2 //executable 163 def I = "b1".U << 3 //cacheable: icache 164 def D = "b1".U << 4 //cacheable: dcache 165 def S = "b1".U << 5 //enable speculative access 166 def A = "b1".U << 6 //enable atomic operation, A imply R & W 167 def C = "b1".U << 7 //if it is cacheable is configable 168 def Reserved = "b0".U 169 170 def apply() = UInt(7.W) 171 172 def read(mode: UInt) = mode(0) 173 def write(mode: UInt) = mode(1) 174 def execute(mode: UInt) = mode(2) 175 def icache(mode: UInt) = mode(3) 176 def dcache(mode: UInt) = mode(4) 177 def speculate(mode: UInt) = mode(5) 178 def atomic(mode: UInt) = mode(6) 179 def configable_cache(mode: UInt) = mode(7) 180 181 def strToMode(s: String) = { 182 var result = 0.U(8.W) 183 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 184 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 185 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 186 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 187 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 188 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 189 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 190 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 191 result 192 } 193 } 194 195 196 object CSROpType { 197 def jmp = "b000".U 198 def wrt = "b001".U 199 def set = "b010".U 200 def clr = "b011".U 201 def wfi = "b100".U 202 def wrti = "b101".U 203 def seti = "b110".U 204 def clri = "b111".U 205 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 206 } 207 208 // jump 209 object JumpOpType { 210 def jal = "b00".U 211 def jalr = "b01".U 212 def auipc = "b10".U 213// def call = "b11_011".U 214// def ret = "b11_100".U 215 def jumpOpisJalr(op: UInt) = op(0) 216 def jumpOpisAuipc(op: UInt) = op(1) 217 } 218 219 object FenceOpType { 220 def fence = "b10000".U 221 def sfence = "b10001".U 222 def fencei = "b10010".U 223 def nofence= "b00000".U 224 } 225 226 object ALUOpType { 227 // shift optype 228 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 229 def sll = "b000_0001".U // sll: src1 << src2 230 231 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 232 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 233 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 234 235 def srl = "b000_0101".U // srl: src1 >> src2 236 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 237 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 238 239 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 240 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 241 242 // RV64 32bit optype 243 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 244 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 245 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 246 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 247 248 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 249 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 250 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 251 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 252 253 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 254 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 255 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 256 def rolw = "b001_1100".U 257 def rorw = "b001_1101".U 258 259 // ADD-op 260 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 261 def add = "b010_0001".U // add: src1 + src2 262 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 263 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 264 265 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 266 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 267 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 268 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 269 270 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 271 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 272 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 273 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 274 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 275 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 276 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 277 278 // SUB-op: src1 - src2 279 def sub = "b011_0000".U 280 def sltu = "b011_0001".U 281 def slt = "b011_0010".U 282 def maxu = "b011_0100".U 283 def minu = "b011_0101".U 284 def max = "b011_0110".U 285 def min = "b011_0111".U 286 287 // branch 288 def beq = "b111_0000".U 289 def bne = "b111_0010".U 290 def blt = "b111_1000".U 291 def bge = "b111_1010".U 292 def bltu = "b111_1100".U 293 def bgeu = "b111_1110".U 294 295 // misc optype 296 def and = "b100_0000".U 297 def andn = "b100_0001".U 298 def or = "b100_0010".U 299 def orn = "b100_0011".U 300 def xor = "b100_0100".U 301 def xnor = "b100_0101".U 302 def orcb = "b100_0110".U 303 304 def sextb = "b100_1000".U 305 def packh = "b100_1001".U 306 def sexth = "b100_1010".U 307 def packw = "b100_1011".U 308 309 def revb = "b101_0000".U 310 def rev8 = "b101_0001".U 311 def pack = "b101_0010".U 312 def orh48 = "b101_0011".U 313 314 def szewl1 = "b101_1000".U 315 def szewl2 = "b101_1001".U 316 def szewl3 = "b101_1010".U 317 def byte2 = "b101_1011".U 318 319 def andlsb = "b110_0000".U 320 def andzexth = "b110_0001".U 321 def orlsb = "b110_0010".U 322 def orzexth = "b110_0011".U 323 def xorlsb = "b110_0100".U 324 def xorzexth = "b110_0101".U 325 def orcblsb = "b110_0110".U 326 def orcbzexth = "b110_0111".U 327 328 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 329 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 330 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 331 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 332 333 def apply() = UInt(FuOpTypeWidth.W) 334 } 335 336 object VSETOpType { 337 val setVlmaxBit = 0 338 val keepVlBit = 1 339 // destTypeBit == 0: write vl to rd 340 // destTypeBit == 1: write vconfig 341 val destTypeBit = 5 342 343 // vsetvli's uop 344 // rs1!=x0, normal 345 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 346 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 347 def uvsetvcfg_xi = "b1010_0000".U 348 def uvsetrd_xi = "b1000_0000".U 349 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 350 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 351 // uop1: w(rd) | vlmax, vtypei -> x[rd] 352 def uvsetvcfg_vlmax_i = "b1010_0001".U 353 def uvsetrd_vlmax_i = "b1000_0001".U 354 // rs1==x0, rd==x0, keep vl, set vtype 355 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 356 def uvsetvcfg_keep_v = "b1010_0010".U 357 358 // vsetvl's uop 359 // rs1!=x0, normal 360 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 361 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 362 def uvsetvcfg_xx = "b0110_0000".U 363 def uvsetrd_xx = "b0100_0000".U 364 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 365 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 366 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 367 def uvsetvcfg_vlmax_x = "b0110_0001".U 368 def uvsetrd_vlmax_x = "b0100_0001".U 369 // rs1==x0, rd==x0, keep vl, set vtype 370 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 371 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 372 def uvmv_v_x = "b0110_0010".U 373 def uvsetvcfg_vv = "b0111_0010".U 374 375 // vsetivli's uop 376 // uop0: w(vconfig) | vli, vtypei -> vconfig 377 // uop1: w(rd) | vli, vtypei -> x[rd] 378 def uvsetvcfg_ii = "b0010_0000".U 379 def uvsetrd_ii = "b0000_0000".U 380 381 def isVsetvl (func: UInt) = func(6) 382 def isVsetvli (func: UInt) = func(7) 383 def isVsetivli(func: UInt) = func(7, 6) === 0.U 384 def isNormal (func: UInt) = func(1, 0) === 0.U 385 def isSetVlmax(func: UInt) = func(setVlmaxBit) 386 def isKeepVl (func: UInt) = func(keepVlBit) 387 // RG: region 388 def writeIntRG(func: UInt) = !func(5) 389 def writeVecRG(func: UInt) = func(5) 390 def readIntRG (func: UInt) = !func(4) 391 def readVecRG (func: UInt) = func(4) 392 // modify fuOpType 393 def keepVl(func: UInt) = func | (1 << keepVlBit).U 394 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 395 } 396 397 object BRUOpType { 398 // branch 399 def beq = "b000_000".U 400 def bne = "b000_001".U 401 def blt = "b000_100".U 402 def bge = "b000_101".U 403 def bltu = "b001_000".U 404 def bgeu = "b001_001".U 405 406 def getBranchType(func: UInt) = func(3, 1) 407 def isBranchInvert(func: UInt) = func(0) 408 } 409 410 object MULOpType { 411 // mul 412 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 413 def mul = "b00000".U 414 def mulh = "b00001".U 415 def mulhsu = "b00010".U 416 def mulhu = "b00011".U 417 def mulw = "b00100".U 418 419 def mulw7 = "b01100".U 420 def isSign(op: UInt) = !op(1) 421 def isW(op: UInt) = op(2) 422 def isH(op: UInt) = op(1, 0) =/= 0.U 423 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 424 } 425 426 object DIVOpType { 427 // div 428 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 429 def div = "b10000".U 430 def divu = "b10010".U 431 def rem = "b10001".U 432 def remu = "b10011".U 433 434 def divw = "b10100".U 435 def divuw = "b10110".U 436 def remw = "b10101".U 437 def remuw = "b10111".U 438 439 def isSign(op: UInt) = !op(1) 440 def isW(op: UInt) = op(2) 441 def isH(op: UInt) = op(0) 442 } 443 444 object MDUOpType { 445 // mul 446 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 447 def mul = "b00000".U 448 def mulh = "b00001".U 449 def mulhsu = "b00010".U 450 def mulhu = "b00011".U 451 def mulw = "b00100".U 452 453 def mulw7 = "b01100".U 454 455 // div 456 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 457 def div = "b10000".U 458 def divu = "b10010".U 459 def rem = "b10001".U 460 def remu = "b10011".U 461 462 def divw = "b10100".U 463 def divuw = "b10110".U 464 def remw = "b10101".U 465 def remuw = "b10111".U 466 467 def isMul(op: UInt) = !op(4) 468 def isDiv(op: UInt) = op(4) 469 470 def isDivSign(op: UInt) = isDiv(op) && !op(1) 471 def isW(op: UInt) = op(2) 472 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 473 def getMulOp(op: UInt) = op(1, 0) 474 } 475 476 object LSUOpType { 477 // load pipeline 478 479 // normal load 480 // Note: bit(1, 0) are size, DO NOT CHANGE 481 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 482 def lb = "b0000".U 483 def lh = "b0001".U 484 def lw = "b0010".U 485 def ld = "b0011".U 486 def lbu = "b0100".U 487 def lhu = "b0101".U 488 def lwu = "b0110".U 489 490 // Zicbop software prefetch 491 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 492 def prefetch_i = "b1000".U // TODO 493 def prefetch_r = "b1001".U 494 def prefetch_w = "b1010".U 495 496 def isPrefetch(op: UInt): Bool = op(3) 497 498 // store pipeline 499 // normal store 500 // bit encoding: | store 00 | size(2bit) | 501 def sb = "b0000".U 502 def sh = "b0001".U 503 def sw = "b0010".U 504 def sd = "b0011".U 505 506 // l1 cache op 507 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 508 def cbo_zero = "b0111".U 509 510 // llc op 511 // bit encoding: | prefetch 11 | suboptype(2bit) | 512 def cbo_clean = "b1100".U 513 def cbo_flush = "b1101".U 514 def cbo_inval = "b1110".U 515 516 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 517 518 // atomics 519 // bit(1, 0) are size 520 // since atomics use a different fu type 521 // so we can safely reuse other load/store's encodings 522 // bit encoding: | optype(4bit) | size (2bit) | 523 def lr_w = "b000010".U 524 def sc_w = "b000110".U 525 def amoswap_w = "b001010".U 526 def amoadd_w = "b001110".U 527 def amoxor_w = "b010010".U 528 def amoand_w = "b010110".U 529 def amoor_w = "b011010".U 530 def amomin_w = "b011110".U 531 def amomax_w = "b100010".U 532 def amominu_w = "b100110".U 533 def amomaxu_w = "b101010".U 534 535 def lr_d = "b000011".U 536 def sc_d = "b000111".U 537 def amoswap_d = "b001011".U 538 def amoadd_d = "b001111".U 539 def amoxor_d = "b010011".U 540 def amoand_d = "b010111".U 541 def amoor_d = "b011011".U 542 def amomin_d = "b011111".U 543 def amomax_d = "b100011".U 544 def amominu_d = "b100111".U 545 def amomaxu_d = "b101011".U 546 547 def size(op: UInt) = op(1,0) 548 } 549 550 object BKUOpType { 551 552 def clmul = "b000000".U 553 def clmulh = "b000001".U 554 def clmulr = "b000010".U 555 def xpermn = "b000100".U 556 def xpermb = "b000101".U 557 558 def clz = "b001000".U 559 def clzw = "b001001".U 560 def ctz = "b001010".U 561 def ctzw = "b001011".U 562 def cpop = "b001100".U 563 def cpopw = "b001101".U 564 565 // 01xxxx is reserve 566 def aes64es = "b100000".U 567 def aes64esm = "b100001".U 568 def aes64ds = "b100010".U 569 def aes64dsm = "b100011".U 570 def aes64im = "b100100".U 571 def aes64ks1i = "b100101".U 572 def aes64ks2 = "b100110".U 573 574 // merge to two instruction sm4ks & sm4ed 575 def sm4ed0 = "b101000".U 576 def sm4ed1 = "b101001".U 577 def sm4ed2 = "b101010".U 578 def sm4ed3 = "b101011".U 579 def sm4ks0 = "b101100".U 580 def sm4ks1 = "b101101".U 581 def sm4ks2 = "b101110".U 582 def sm4ks3 = "b101111".U 583 584 def sha256sum0 = "b110000".U 585 def sha256sum1 = "b110001".U 586 def sha256sig0 = "b110010".U 587 def sha256sig1 = "b110011".U 588 def sha512sum0 = "b110100".U 589 def sha512sum1 = "b110101".U 590 def sha512sig0 = "b110110".U 591 def sha512sig1 = "b110111".U 592 593 def sm3p0 = "b111000".U 594 def sm3p1 = "b111001".U 595 } 596 597 object BTBtype { 598 def B = "b00".U // branch 599 def J = "b01".U // jump 600 def I = "b10".U // indirect 601 def R = "b11".U // return 602 603 def apply() = UInt(2.W) 604 } 605 606 object SelImm { 607 def IMM_X = "b0111".U 608 def IMM_S = "b1110".U 609 def IMM_SB = "b0001".U 610 def IMM_U = "b0010".U 611 def IMM_UJ = "b0011".U 612 def IMM_I = "b0100".U 613 def IMM_Z = "b0101".U 614 def INVALID_INSTR = "b0110".U 615 def IMM_B6 = "b1000".U 616 617 def IMM_OPIVIS = "b1001".U 618 def IMM_OPIVIU = "b1010".U 619 def IMM_VSETVLI = "b1100".U 620 def IMM_VSETIVLI = "b1101".U 621 def IMM_LUI32 = "b1011".U 622 623 def X = BitPat("b0000") 624 625 def apply() = UInt(4.W) 626 627 def mkString(immType: UInt) : String = { 628 val strMap = Map( 629 IMM_S.litValue -> "S", 630 IMM_SB.litValue -> "SB", 631 IMM_U.litValue -> "U", 632 IMM_UJ.litValue -> "UJ", 633 IMM_I.litValue -> "I", 634 IMM_Z.litValue -> "Z", 635 IMM_B6.litValue -> "B6", 636 IMM_OPIVIS.litValue -> "VIS", 637 IMM_OPIVIU.litValue -> "VIU", 638 IMM_VSETVLI.litValue -> "VSETVLI", 639 IMM_VSETIVLI.litValue -> "VSETIVLI", 640 IMM_LUI32.litValue -> "LUI32", 641 INVALID_INSTR.litValue -> "INVALID", 642 ) 643 strMap(immType.litValue) 644 } 645 } 646 647 object UopSplitType { 648 def SCA_SIM = "b000000".U // 649 def VSET = "b010001".U // dirty: vset 650 def VEC_VVV = "b010010".U // VEC_VVV 651 def VEC_VXV = "b010011".U // VEC_VXV 652 def VEC_0XV = "b010100".U // VEC_0XV 653 def VEC_VVW = "b010101".U // VEC_VVW 654 def VEC_WVW = "b010110".U // VEC_WVW 655 def VEC_VXW = "b010111".U // VEC_VXW 656 def VEC_WXW = "b011000".U // VEC_WXW 657 def VEC_WVV = "b011001".U // VEC_WVV 658 def VEC_WXV = "b011010".U // VEC_WXV 659 def VEC_EXT2 = "b011011".U // VF2 0 -> V 660 def VEC_EXT4 = "b011100".U // VF4 0 -> V 661 def VEC_EXT8 = "b011101".U // VF8 0 -> V 662 def VEC_VVM = "b011110".U // VEC_VVM 663 def VEC_VXM = "b011111".U // VEC_VXM 664 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 665 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 666 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 667 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 668 def VEC_VRED = "b100100".U // VEC_VRED 669 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 670 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 671 def VEC_M0X = "b101001".U // VEC_M0X 0MV 672 def VEC_MVV = "b101010".U // VEC_MVV VMV 673 def VEC_M0X_VFIRST = "b101011".U // 674 def VEC_VWW = "b101100".U // 675 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 676 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 677 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 678 def VEC_COMPRESS = "b110000".U // vcompress.vm 679 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 680 def VEC_S_LDST = "b110010".U // vector strided load/store 681 def VEC_I_LDST = "b110011".U // vector indexed load/store 682 def VEC_VFV = "b111000".U // VEC_VFV 683 def VEC_VFW = "b111001".U // VEC_VFW 684 def VEC_WFW = "b111010".U // VEC_WVW 685 def VEC_VFM = "b111011".U // VEC_VFM 686 def VEC_VFRED = "b111100".U // VEC_VFRED 687 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 688 def VEC_M0M = "b000000".U // VEC_M0M 689 def VEC_MMM = "b000000".U // VEC_MMM 690 def VEC_MVNR = "b000100".U // vmvnr 691 def dummy = "b111111".U 692 693 def X = BitPat("b000000") 694 695 def apply() = UInt(6.W) 696 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 697 } 698 699 object ExceptionNO { 700 def instrAddrMisaligned = 0 701 def instrAccessFault = 1 702 def illegalInstr = 2 703 def breakPoint = 3 704 def loadAddrMisaligned = 4 705 def loadAccessFault = 5 706 def storeAddrMisaligned = 6 707 def storeAccessFault = 7 708 def ecallU = 8 709 def ecallS = 9 710 def ecallM = 11 711 def instrPageFault = 12 712 def loadPageFault = 13 713 // def singleStep = 14 714 def storePageFault = 15 715 def priorities = Seq( 716 breakPoint, // TODO: different BP has different priority 717 instrPageFault, 718 instrAccessFault, 719 illegalInstr, 720 instrAddrMisaligned, 721 ecallM, ecallS, ecallU, 722 storeAddrMisaligned, 723 loadAddrMisaligned, 724 storePageFault, 725 loadPageFault, 726 storeAccessFault, 727 loadAccessFault 728 ) 729 def all = priorities.distinct.sorted 730 def frontendSet = Seq( 731 instrAddrMisaligned, 732 instrAccessFault, 733 illegalInstr, 734 instrPageFault 735 ) 736 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 737 val new_vec = Wire(ExceptionVec()) 738 new_vec.foreach(_ := false.B) 739 select.foreach(i => new_vec(i) := vec(i)) 740 new_vec 741 } 742 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 743 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 744 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 745 partialSelect(vec, fuConfig.exceptionOut) 746 } 747 748 object TopDownCounters extends Enumeration { 749 val NoStall = Value("NoStall") // Base 750 // frontend 751 val OverrideBubble = Value("OverrideBubble") 752 val FtqUpdateBubble = Value("FtqUpdateBubble") 753 // val ControlRedirectBubble = Value("ControlRedirectBubble") 754 val TAGEMissBubble = Value("TAGEMissBubble") 755 val SCMissBubble = Value("SCMissBubble") 756 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 757 val RASMissBubble = Value("RASMissBubble") 758 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 759 val OtherRedirectBubble = Value("OtherRedirectBubble") 760 val FtqFullStall = Value("FtqFullStall") 761 762 val ICacheMissBubble = Value("ICacheMissBubble") 763 val ITLBMissBubble = Value("ITLBMissBubble") 764 val BTBMissBubble = Value("BTBMissBubble") 765 val FetchFragBubble = Value("FetchFragBubble") 766 767 // backend 768 // long inst stall at rob head 769 val DivStall = Value("DivStall") // int div, float div/sqrt 770 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 771 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 772 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 773 // freelist full 774 val IntFlStall = Value("IntFlStall") 775 val FpFlStall = Value("FpFlStall") 776 // dispatch queue full 777 val IntDqStall = Value("IntDqStall") 778 val FpDqStall = Value("FpDqStall") 779 val LsDqStall = Value("LsDqStall") 780 781 // memblock 782 val LoadTLBStall = Value("LoadTLBStall") 783 val LoadL1Stall = Value("LoadL1Stall") 784 val LoadL2Stall = Value("LoadL2Stall") 785 val LoadL3Stall = Value("LoadL3Stall") 786 val LoadMemStall = Value("LoadMemStall") 787 val StoreStall = Value("StoreStall") // include store tlb miss 788 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 789 790 // xs replay (different to gem5) 791 val LoadVioReplayStall = Value("LoadVioReplayStall") 792 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 793 794 // bad speculation 795 val ControlRecoveryStall = Value("ControlRecoveryStall") 796 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 797 val OtherRecoveryStall = Value("OtherRecoveryStall") 798 799 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 800 801 val OtherCoreStall = Value("OtherCoreStall") 802 803 val NumStallReasons = Value("NumStallReasons") 804 } 805} 806