1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19import xiangshan.backend.fu.vector.Bundles.VSew 20 21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 override def shouldBeInlined: Boolean = false 23 24 implicit val iqParams = params 25 lazy val module: IssueQueueImp = iqParams.schdType match { 26 case IntScheduler() => new IssueQueueIntImp(this) 27 case VfScheduler() => new IssueQueueVfImp(this) 28 case MemScheduler() => 29 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 30 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 31 else new IssueQueueIntImp(this) 32 case _ => null 33 } 34} 35 36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 37 val empty = Output(Bool()) 38 val full = Output(Bool()) 39 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 40 val leftVec = Output(Vec(numEnq + 1, Bool())) 41} 42 43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 44 45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 46 // Inputs 47 val flush = Flipped(ValidIO(new Redirect)) 48 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 49 50 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 56 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 57 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 58 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 59 val og0Cancel = Input(ExuOH(backendParams.numExu)) 60 val og1Cancel = Input(ExuOH(backendParams.numExu)) 61 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 62 63 // Outputs 64 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 65 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 66 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 67 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 68 69 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 70 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 71} 72 73class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 74 extends LazyModuleImp(wrapper) 75 with HasXSParameter { 76 77 override def desiredName: String = s"${params.getIQName}" 78 79 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 80 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 81 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 82 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 83 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 84 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 85 86 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 87 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 88 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 89 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 90 91 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 92 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 93 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 94 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 95 val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap) 96 97 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}") 98 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 99 lazy val io = IO(new IssueQueueIO()) 100 101 // Modules 102 val entries = Module(new Entries) 103 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 104 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 105 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 106 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 107 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 108 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 109 110 class WakeupQueueFlush extends Bundle { 111 val redirect = ValidIO(new Redirect) 112 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 113 val og0Fail = Output(Bool()) 114 val og1Fail = Output(Bool()) 115 } 116 117 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 118 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 119 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 120 val ogFailFlush = stage match { 121 case 1 => flush.og0Fail 122 case 2 => flush.og1Fail 123 case _ => false.B 124 } 125 redirectFlush || loadDependencyFlush || ogFailFlush 126 } 127 128 private def modificationFunc(exuInput: ExuInput): ExuInput = { 129 val newExuInput = WireDefault(exuInput) 130 newExuInput.loadDependency match { 131 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 132 case None => 133 } 134 newExuInput 135 } 136 137 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 138 val lastExuInput = WireDefault(exuInput) 139 val newExuInput = WireDefault(newInput) 140 newExuInput.elements.foreach { case (name, data) => 141 if (lastExuInput.elements.contains(name)) { 142 data := lastExuInput.elements(name) 143 } 144 } 145 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 146 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 147 } 148 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 149 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 150 } 151 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 152 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 153 } 154 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 155 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 156 } 157 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 158 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 159 } 160 newExuInput 161 } 162 163 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 164 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 165 ))} 166 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 167 168 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 169 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 170 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 171 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 172 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 173 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 174 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 175 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 176 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 177 val s0_enqValidVec = io.enq.map(_.valid) 178 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 179 val s0_enqNotFlush = !io.flush.valid 180 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 181 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 182 183 184 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 185 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 186 187 val validVec = VecInit(entries.io.valid.asBools) 188 val canIssueVec = VecInit(entries.io.canIssue.asBools) 189 dontTouch(canIssueVec) 190 val deqFirstIssueVec = entries.io.isFirstIssue 191 192 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 193 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 194 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 195 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 196 // (entryIdx)(srcIdx)(exuIdx) 197 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 198 val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer 199 200 // (deqIdx)(srcIdx)(exuIdx) 201 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 202 val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 203 204 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 205 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 206 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 209 //deq 210 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 211 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 212 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 213 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 214 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 215 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 216 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 217 218 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 219 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 220 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 221 222 //trans 223 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 224 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 225 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 226 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 227 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 228 229 /** 230 * Connection of [[entries]] 231 */ 232 entries.io match { case entriesIO: EntriesIO => 233 entriesIO.flush := io.flush 234 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 235 enq.valid := s0_doEnqSelValidVec(enqIdx) 236 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 237 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 238 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 239 for(j <- 0 until numLsrc) { 240 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 241 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 242 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 243 enq.bits.status.srcStatus(j).dataSources.value := Mux( 244 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 245 DataSource.zero, 246 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 247 ) 248 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 249 if(params.hasIQWakeUp) { 250 enq.bits.status.srcStatus(j).srcTimer.get := 0.U(3.W) 251 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 252 } 253 } 254 enq.bits.status.blocked := false.B 255 enq.bits.status.issued := false.B 256 enq.bits.status.firstIssue := false.B 257 enq.bits.status.issueTimer := "b10".U 258 enq.bits.status.deqPortIdx := 0.U 259 if (params.inIntSchd && params.AluCnt > 0) { 260 // dirty code for lui+addi(w) fusion 261 val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32 262 val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0)) 263 enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm)) 264 } 265 else if (params.isLdAddrIQ || params.isHyAddrIQ) { 266 // dirty code for fused_lui_load 267 val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType) 268 enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm)) 269 } 270 else { 271 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 272 } 273 enq.bits.payload := s0_enqBits(enqIdx) 274 } 275 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 276 og0Resp := io.og0Resp(i) 277 } 278 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 279 og1Resp := io.og1Resp(i) 280 } 281 if (params.isLdAddrIQ || params.isHyAddrIQ) { 282 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 283 finalIssueResp := io.finalIssueResp.get(i) 284 } 285 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 286 memAddrIssueResp := io.memAddrIssueResp.get(i) 287 } 288 } 289 if (params.isVecLduIQ) { 290 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 291 resp := io.vecLoadIssueResp.get(i) 292 } 293 } 294 for(deqIdx <- 0 until params.numDeq) { 295 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 296 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 297 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 298 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 299 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 300 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 301 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 302 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 303 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 304 } 305 entriesIO.wakeUpFromWB := io.wakeupFromWB 306 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 307 entriesIO.og0Cancel := io.og0Cancel 308 entriesIO.og1Cancel := io.og1Cancel 309 entriesIO.ldCancel := io.ldCancel 310 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 311 //output 312 fuTypeVec := entriesIO.fuType 313 deqEntryVec := entriesIO.deqEntry 314 cancelDeqVec := entriesIO.cancelDeqVec 315 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 316 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 317 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 318 } 319 320 321 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 322 323 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 324 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 325 ).reverse) 326 327 // if deq port can accept the uop 328 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 329 Cat(fuTypeVec.map(fuType => 330 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 331 ).reverse) 332 } 333 334 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 335 fuTypeVec.map(fuType => 336 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 337 } 338 339 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 340 val mergeFuBusy = { 341 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 342 else canIssueVec.asUInt 343 } 344 val mergeIntWbBusy = { 345 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 346 else mergeFuBusy 347 } 348 val mergeVfWbBusy = { 349 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 350 else mergeIntWbBusy 351 } 352 merge := mergeVfWbBusy 353 } 354 355 deqCanIssue.zipWithIndex.foreach { case (req, i) => 356 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 357 } 358 dontTouch(fuTypeVec) 359 dontTouch(canIssueMergeAllBusy) 360 dontTouch(deqCanIssue) 361 362 if (params.numDeq == 2) { 363 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 364 } 365 366 if (params.numDeq == 2 && params.deqFuSame) { 367 val subDeqPolicy = Module(new DeqPolicy()) 368 369 enqEntryOldestSel := DontCare 370 371 if (params.isAllComp || params.isAllSimp) { 372 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 373 enq = othersEntryEnqSelVec.get, 374 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 375 ) 376 othersEntryOldestSel(1) := DontCare 377 378 subDeqPolicy.io.request := subDeqRequest.get 379 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 380 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 381 } 382 else { 383 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 384 simpAgeDetectRequest.get(1) := DontCare 385 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 386 if (params.numEnq == 2) { 387 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 388 } 389 390 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 391 enq = simpEntryEnqSelVec.get, 392 canIssue = simpAgeDetectRequest.get 393 ) 394 395 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 396 enq = compEntryEnqSelVec.get, 397 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 398 ) 399 compEntryOldestSel.get(1) := DontCare 400 401 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 402 othersEntryOldestSel(0).bits := Cat( 403 compEntryOldestSel.get(0).bits, 404 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 405 ) 406 othersEntryOldestSel(1) := DontCare 407 408 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 409 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 410 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 411 } 412 413 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 414 415 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 416 deqSelValidVec(1) := subDeqSelValidVec.get(0) 417 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 418 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 419 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 420 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 421 422 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 423 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 424 selOH := deqOH 425 } 426 } 427 else { 428 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 429 enq = VecInit(s0_doEnqSelValidVec), 430 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 431 ) 432 433 if (params.isAllComp || params.isAllSimp) { 434 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 435 enq = othersEntryEnqSelVec.get, 436 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 437 ) 438 439 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 440 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 441 selValid := false.B 442 selOH := 0.U.asTypeOf(selOH) 443 } else { 444 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 445 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 446 } 447 } 448 } 449 else { 450 othersEntryOldestSel := DontCare 451 452 deqCanIssue.zipWithIndex.foreach { case (req, i) => 453 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 454 } 455 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 456 if (params.numEnq == 2) { 457 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 458 } 459 460 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 461 enq = simpEntryEnqSelVec.get, 462 canIssue = simpAgeDetectRequest.get 463 ) 464 465 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 466 enq = compEntryEnqSelVec.get, 467 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 468 ) 469 470 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 471 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 472 selValid := false.B 473 selOH := 0.U.asTypeOf(selOH) 474 } else { 475 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 476 selOH := Cat( 477 compEntryOldestSel.get(i).bits, 478 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 479 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 480 ) 481 } 482 } 483 } 484 485 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 486 selValid := deqValid && deqBeforeDly(i).ready 487 selOH := deqOH 488 } 489 } 490 491 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 492 493 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 494 deqResp.valid := finalDeqSelValidVec(i) 495 deqResp.bits.resp := RespType.success 496 deqResp.bits.robIdx := DontCare 497 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 498 deqResp.bits.uopIdx.foreach(_ := DontCare) 499 } 500 501 //fuBusyTable 502 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 503 if(busyTableWrite.nonEmpty) { 504 val btwr = busyTableWrite.get 505 val btrd = busyTableRead.get 506 btwr.io.in.deqResp := toBusyTableDeqResp(i) 507 btwr.io.in.og0Resp := io.og0Resp(i) 508 btwr.io.in.og1Resp := io.og1Resp(i) 509 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 510 btrd.io.in.fuTypeRegVec := fuTypeVec 511 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 512 } 513 else { 514 fuBusyTableMask(i) := 0.U(params.numEntries.W) 515 } 516 } 517 518 //wbfuBusyTable write 519 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 520 if(busyTableWrite.nonEmpty) { 521 val btwr = busyTableWrite.get 522 val bt = busyTable.get 523 val dq = deqResp.get 524 btwr.io.in.deqResp := toBusyTableDeqResp(i) 525 btwr.io.in.og0Resp := io.og0Resp(i) 526 btwr.io.in.og1Resp := io.og1Resp(i) 527 bt := btwr.io.out.fuBusyTable 528 dq := btwr.io.out.deqRespSet 529 } 530 } 531 532 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 533 if (busyTableWrite.nonEmpty) { 534 val btwr = busyTableWrite.get 535 val bt = busyTable.get 536 val dq = deqResp.get 537 btwr.io.in.deqResp := toBusyTableDeqResp(i) 538 btwr.io.in.og0Resp := io.og0Resp(i) 539 btwr.io.in.og1Resp := io.og1Resp(i) 540 bt := btwr.io.out.fuBusyTable 541 dq := btwr.io.out.deqRespSet 542 } 543 } 544 545 //wbfuBusyTable read 546 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 547 if(busyTableRead.nonEmpty) { 548 val btrd = busyTableRead.get 549 val bt = busyTable.get 550 btrd.io.in.fuBusyTable := bt 551 btrd.io.in.fuTypeRegVec := fuTypeVec 552 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 553 } 554 else { 555 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 556 } 557 } 558 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 559 if (busyTableRead.nonEmpty) { 560 val btrd = busyTableRead.get 561 val bt = busyTable.get 562 btrd.io.in.fuBusyTable := bt 563 btrd.io.in.fuTypeRegVec := fuTypeVec 564 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 565 } 566 else { 567 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 568 } 569 } 570 571 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 572 wakeUpQueueOption.foreach { 573 wakeUpQueue => 574 val flush = Wire(new WakeupQueueFlush) 575 flush.redirect := io.flush 576 flush.ldCancel := io.ldCancel 577 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 578 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 579 wakeUpQueue.io.flush := flush 580 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 581 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 582 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 583 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 584 } 585 } 586 587 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 588 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 589 deq.bits.addrOH := finalDeqSelOHVec(i) 590 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 591 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 592 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 593 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 594 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 595 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 596 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 597 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 598 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 599 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 600 601 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 602 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 603 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 604 deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i)) 605 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 606 deq.bits.common.src := DontCare 607 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 608 609 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 610 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 611 rf.foreach(_.addr := psrc) 612 rf.foreach(_.srcType := srcType) 613 } 614 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 615 sink := source 616 } 617 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 618 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 619 620 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 621 deq.bits.common.perfDebugInfo.selectTime := GTimer() 622 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 623 } 624 625 private val deqShift = WireDefault(deqBeforeDly) 626 deqShift.zip(deqBeforeDly).foreach { 627 case (shifted, original) => 628 original.ready := shifted.ready // this will not cause combinational loop 629 shifted.bits.common.loadDependency.foreach( 630 _ := original.bits.common.loadDependency.get.map(_ << 1) 631 ) 632 } 633 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 634 NewPipelineConnect( 635 deq, deqDly, deqDly.valid, 636 false.B, 637 Option("Scheduler2DataPathPipe") 638 ) 639 } 640 if(backendParams.debugEn) { 641 dontTouch(io.deqDelay) 642 } 643 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 644 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 645 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 646 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 647 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 648 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 649 } else if (wakeUpQueues(i).nonEmpty) { 650 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 651 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 652 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 653 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 654 } else { 655 wakeup.valid := false.B 656 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 657 wakeup.bits.is0Lat := 0.U 658 } 659 if (wakeUpQueues(i).nonEmpty) { 660 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 661 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 662 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 663 } 664 665 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 666 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 667 } 668 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 669 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 670 } 671 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 672 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 673 } 674 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 675 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 676 } 677 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 678 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 679 } 680 } 681 682 // Todo: better counter implementation 683 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 684 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 685 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 686 private val enqEntryValidCntDeq0 = PopCount( 687 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 688 ) 689 private val othersValidCntDeq0 = PopCount( 690 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 691 ) 692 private val enqEntryValidCntDeq1 = PopCount( 693 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 694 ) 695 private val othersValidCntDeq1 = PopCount( 696 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 697 ) 698 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 699 io.enq.map(_.bits.fuType).map(fuType => 700 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 701 } 702 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 703 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 704 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 705 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 706 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 707 for (i <- 0 until params.numEnq) { 708 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 709 } 710 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 711 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 712 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 713 } 714 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 715 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 716 717 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 718 io.status.empty := !Cat(validVec).orR 719 io.status.full := othersCanotIn 720 io.status.validCnt := PopCount(validVec) 721 722 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 723 Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 724 } 725 726 // issue perf counter 727 // enq count 728 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 729 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 730 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 731 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 732 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 733 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 734 // valid count 735 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 736 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 737 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 738 // only split when more than 1 func type 739 if (params.getFuCfgs.size > 0) { 740 for (t <- FuType.functionNameMap.keys) { 741 val fuName = FuType.functionNameMap(t) 742 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 743 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 744 } 745 } 746 } 747 // ready instr count 748 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 749 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 750 // only split when more than 1 func type 751 if (params.getFuCfgs.size > 0) { 752 for (t <- FuType.functionNameMap.keys) { 753 val fuName = FuType.functionNameMap(t) 754 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 755 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 756 } 757 } 758 } 759 760 // deq instr count 761 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 762 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 763 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 764 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 765 766 // deq instr data source count 767 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 768 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 769 }.reduce(_ +& _)) 770 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 771 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 772 }.reduce(_ +& _)) 773 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 774 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 775 }.reduce(_ +& _)) 776 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 777 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 778 }.reduce(_ +& _)) 779 780 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 781 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 782 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 783 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 784 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 785 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 786 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 787 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 788 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 789 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 790 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 791 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 792 793 // deq instr data source count for each futype 794 for (t <- FuType.functionNameMap.keys) { 795 val fuName = FuType.functionNameMap(t) 796 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 797 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 798 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 799 }.reduce(_ +& _)) 800 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 801 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 802 }.reduce(_ +& _)) 803 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 804 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 805 }.reduce(_ +& _)) 806 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 807 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 808 }.reduce(_ +& _)) 809 810 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 811 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 812 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 813 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 814 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 815 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 816 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 817 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 818 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 819 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 820 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 821 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 822 } 823 } 824 825 // cancel instr count 826 if (params.hasIQWakeUp) { 827 val cancelVec: Vec[Bool] = entries.io.cancel.get 828 XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2))) 829 XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1) 830 for (t <- FuType.functionNameMap.keys) { 831 val fuName = FuType.functionNameMap(t) 832 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 833 XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U })) 834 XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1) 835 } 836 } 837 } 838} 839 840class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 841 val fastMatch = UInt(backendParams.LduCnt.W) 842 val fastImm = UInt(12.W) 843} 844 845class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 846 847class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 848 extends IssueQueueImp(wrapper) 849{ 850 io.suggestName("none") 851 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 852 853 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 854 deq.bits.common.pc.foreach(_ := DontCare) 855 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 856 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 857 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 858 deq.bits.common.predictInfo.foreach(x => { 859 x.target := DontCare 860 x.taken := deqEntryVec(i).bits.payload.pred_taken 861 }) 862 // for std 863 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 864 // for i2f 865 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 866 }} 867} 868 869class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 870 extends IssueQueueImp(wrapper) 871{ 872 s0_enqBits.foreach{ x => 873 x.srcType(3) := SrcType.vp // v0: mask src 874 x.srcType(4) := SrcType.vp // vl&vtype 875 } 876 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 877 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 878 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 879 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 880 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 881 }} 882} 883 884class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 885 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 886 887 // TODO: is still needed? 888 val checkWait = new Bundle { 889 val stIssuePtr = Input(new SqPtr) 890 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 891 } 892 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 893 894 // load wakeup 895 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 896 897 // vector 898 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 899 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 900} 901 902class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 903 val memIO = Some(new IssueQueueMemBundle) 904} 905 906class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 907 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 908 909 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 910 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 911 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 912 913 io.suggestName("none") 914 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 915 private val memIO = io.memIO.get 916 917 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 918 919 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 920 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 921 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 922 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 923 slowResp.bits.fuType := DontCare 924 } 925 926 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 927 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 928 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 929 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 930 fastResp.bits.fuType := DontCare 931 } 932 933 // load wakeup 934 val loadWakeUpIter = memIO.loadWakeUp.iterator 935 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 936 if (param.hasLoadExu) { 937 require(wakeUpQueues(i).isEmpty) 938 val uop = loadWakeUpIter.next() 939 940 wakeup.valid := GatedValidRegNext(uop.fire) 941 wakeup.bits.rfWen := GatedValidRegNext(uop.bits.rfWen && uop.fire) 942 wakeup.bits.fpWen := GatedValidRegNext(uop.bits.fpWen && uop.fire) 943 wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire) 944 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 945 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 946 947 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen && uop.fire))) 948 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen && uop.fire))) 949 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire))) 950 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 951 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 952 953 wakeup.bits.is0Lat := 0.U 954 } 955 } 956 require(!loadWakeUpIter.hasNext) 957 958 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 959 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 960 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 961 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 962 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 963 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 964 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 965 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 966 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 967 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 968 } 969} 970 971class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 972 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 973 974 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 975 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 976 977 io.suggestName("none") 978 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 979 private val memIO = io.memIO.get 980 981 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 982 983 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 984 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 985 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 986 (if (j < i) !valid(j) || compareVec(i)(j) 987 else if (j == i) valid(i) 988 else !valid(j) || !compareVec(j)(i)) 989 )).andR)) 990 resultOnehot 991 } 992 993 s0_enqBits.foreach{ x => 994 x.srcType(3) := SrcType.vp // v0: mask src 995 x.srcType(4) := SrcType.vp // vl&vtype 996 } 997 998 for (i <- entries.io.enq.indices) { 999 entries.io.enq(i).bits.status match { case enqData => 1000 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1001 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1002 // MemAddrIQ also handle vector insts 1003 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1004 enqData.blocked := false.B 1005 } 1006 } 1007 1008 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1009 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1010 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1011 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1012 slowResp.bits.fuType := DontCare 1013 slowResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get 1014 } 1015 1016 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1017 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1018 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1019 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1020 fastResp.bits.fuType := DontCare 1021 fastResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get 1022 } 1023 1024 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1025 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1026 1027 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1028 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1029 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1030 deq.bits.common.numLsElem.get := deqEntryVec(i).bits.status.vecMem.get.numLsElem 1031 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1032 if (params.isVecLduIQ) { 1033 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1034 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1035 } 1036 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1037 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1038 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1039 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1040 } 1041 1042 io.vecLoadIssueResp.foreach(dontTouch(_)) 1043} 1044