1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val canRobCompress = Bool() 81 val selImm = SelImm() 82 val imm = UInt(ImmUnion.maxLen.W) 83 val fpu = new FPUCtrlSignals 84 val vpu = new VPUCtrlSignals 85 val vlsInstr = Bool() 86 val wfflags = Bool() 87 val isMove = Bool() 88 val uopIdx = UopIdx() 89 val uopSplitType = UopSplitType() 90 val isVset = Bool() 91 val firstUop = Bool() 92 val lastUop = Bool() 93 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 94 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 95 val commitType = CommitType() // Todo: remove it 96 97 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 98 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 99 100 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 101 val decoder: Seq[UInt] = ListLookup( 102 inst, XDecode.decodeDefault.map(bitPatToUInt), 103 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 104 ) 105 allSignals zip decoder foreach { case (s, d) => s := d } 106 this 107 } 108 109 def isSoftPrefetch: Bool = { 110 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 111 } 112 113 def connectStaticInst(source: StaticInst): Unit = { 114 for ((name, data) <- this.elements) { 115 if (source.elements.contains(name)) { 116 data := source.elements(name) 117 } 118 } 119 } 120 } 121 122 // DecodedInst --[Rename]--> DynInst 123 class DynInst(implicit p: Parameters) extends XSBundle { 124 def numSrc = backendParams.numSrc 125 // passed from StaticInst 126 val instr = UInt(32.W) 127 val pc = UInt(VAddrBits.W) 128 val foldpc = UInt(MemPredPCWidth.W) 129 val exceptionVec = ExceptionVec() 130 val trigger = new TriggerCf 131 val preDecodeInfo = new PreDecodeInfo 132 val pred_taken = Bool() 133 val crossPageIPFFix = Bool() 134 val ftqPtr = new FtqPtr 135 val ftqOffset = UInt(log2Up(PredictWidth).W) 136 // passed from DecodedInst 137 val srcType = Vec(numSrc, SrcType()) 138 val lsrc = Vec(numSrc, UInt(6.W)) 139 val ldest = UInt(6.W) 140 val fuType = FuType() 141 val fuOpType = FuOpType() 142 val rfWen = Bool() 143 val fpWen = Bool() 144 val vecWen = Bool() 145 val isXSTrap = Bool() 146 val waitForward = Bool() // no speculate execution 147 val blockBackward = Bool() 148 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 149 val canRobCompress = Bool() 150 val selImm = SelImm() 151 val imm = UInt(XLEN.W) // Todo: check if it need minimized 152 val fpu = new FPUCtrlSignals 153 val vpu = new VPUCtrlSignals 154 val vlsInstr = Bool() 155 val wfflags = Bool() 156 val isMove = Bool() 157 val uopIdx = UopIdx() 158 val isVset = Bool() 159 val firstUop = Bool() 160 val lastUop = Bool() 161 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 162 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 163 val commitType = CommitType() 164 // rename 165 val srcState = Vec(numSrc, SrcState()) 166 val dataSource = Vec(numSrc, DataSource()) 167 val l1ExuOH = Vec(numSrc, ExuOH()) 168 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 169 val pdest = UInt(PhyRegIdxWidth.W) 170 val robIdx = new RobPtr 171 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 172 val dirtyFs = Bool() 173 174 val eliminatedMove = Bool() 175 // Take snapshot at this CFI inst 176 val snapshot = Bool() 177 val debugInfo = new PerfDebugInfo 178 val storeSetHit = Bool() // inst has been allocated an store set 179 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 180 // Load wait is needed 181 // load inst will not be executed until former store (predicted by mdp) addr calcuated 182 val loadWaitBit = Bool() 183 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 184 // load inst will not be executed until ALL former store addr calcuated 185 val loadWaitStrict = Bool() 186 val ssid = UInt(SSIDWidth.W) 187 // Todo 188 val lqIdx = new LqPtr 189 val sqIdx = new SqPtr 190 // debug module 191 val singleStep = Bool() 192 // schedule 193 val replayInst = Bool() 194 195 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 196 def isLUI32: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_LUI32 197 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 198 199 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 200 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 201 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 202 203 def srcIsReady: Vec[Bool] = { 204 VecInit(this.srcType.zip(this.srcState).map { 205 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 206 }) 207 } 208 209 def clearExceptions( 210 exceptionBits: Seq[Int] = Seq(), 211 flushPipe : Boolean = false, 212 replayInst : Boolean = false 213 ): DynInst = { 214 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 215 if (!flushPipe) { this.flushPipe := false.B } 216 if (!replayInst) { this.replayInst := false.B } 217 this 218 } 219 220 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 221 } 222 223 trait BundleSource { 224 var wakeupSource = "undefined" 225 var idx = 0 226 } 227 228 /** 229 * 230 * @param pregIdxWidth index width of preg 231 * @param exuIndices exu indices of wakeup bundle 232 */ 233 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 234 val rfWen = Bool() 235 val fpWen = Bool() 236 val vecWen = Bool() 237 val pdest = UInt(pregIdxWidth.W) 238 239 /** 240 * @param successor Seq[(psrc, srcType)] 241 * @return Seq[if wakeup psrc] 242 */ 243 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 244 successor.map { case (thatPsrc, srcType) => 245 val pdestMatch = pdest === thatPsrc 246 pdestMatch && ( 247 SrcType.isFp(srcType) && this.fpWen || 248 SrcType.isXp(srcType) && this.rfWen || 249 SrcType.isVp(srcType) && this.vecWen 250 ) && valid 251 } 252 } 253 254 def hasOnlyOneSource: Boolean = exuIndices.size == 1 255 256 def hasMultiSources: Boolean = exuIndices.size > 1 257 258 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 259 260 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 261 262 def exuIdx: Int = { 263 require(hasOnlyOneSource) 264 this.exuIndices.head 265 } 266 } 267 268 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 269 270 } 271 272 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 273 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 274 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 275 this.rfWen := exuInput.rfWen.getOrElse(false.B) 276 this.fpWen := exuInput.fpWen.getOrElse(false.B) 277 this.vecWen := exuInput.vecWen.getOrElse(false.B) 278 this.pdest := exuInput.pdest 279 } 280 281 def fromExuInput(exuInput: ExuInput): Unit = { 282 this.rfWen := exuInput.rfWen.getOrElse(false.B) 283 this.fpWen := exuInput.fpWen.getOrElse(false.B) 284 this.vecWen := exuInput.vecWen.getOrElse(false.B) 285 this.pdest := exuInput.pdest 286 } 287 } 288 289 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 290 // vtype 291 val vill = Bool() 292 val vma = Bool() // 1: agnostic, 0: undisturbed 293 val vta = Bool() // 1: agnostic, 0: undisturbed 294 val vsew = VSew() 295 val vlmul = VLmul() // 1/8~8 --> -3~3 296 297 val vm = Bool() // 0: need v0.t 298 val vstart = Vl() 299 300 // float rounding mode 301 val frm = Frm() 302 // scalar float instr and vector float reduction 303 val fpu = Fpu() 304 // vector fix int rounding mode 305 val vxrm = Vxrm() 306 // vector uop index, exclude other non-vector uop 307 val vuopIdx = UopIdx() 308 val lastUop = Bool() 309 // maybe used if data dependancy 310 val vmask = UInt(MaskSrcData().dataWidth.W) 311 val vl = Vl() 312 313 // vector load/store 314 val nf = Nf() 315 val veew = VEew() 316 317 val isReverse = Bool() // vrsub, vrdiv 318 val isExt = Bool() 319 val isNarrow = Bool() 320 val isDstMask = Bool() // vvm, vvvm, mmm 321 val isOpMask = Bool() // vmand, vmnand 322 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 323 324 def vtype: VType = { 325 val res = Wire(VType()) 326 res.illegal := this.vill 327 res.vma := this.vma 328 res.vta := this.vta 329 res.vsew := this.vsew 330 res.vlmul := this.vlmul 331 res 332 } 333 334 def vconfig: VConfig = { 335 val res = Wire(VConfig()) 336 res.vtype := this.vtype 337 res.vl := this.vl 338 res 339 } 340 } 341 342 // DynInst --[IssueQueue]--> DataPath 343 class IssueQueueIssueBundle( 344 iqParams: IssueBlockParams, 345 val exuParams: ExeUnitParams, 346 )(implicit 347 p: Parameters 348 ) extends Bundle { 349 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 350 // check which set both have fp and vec and remove fp 351 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 352 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 353 else set 354 ) 355 356 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 357 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 358 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 359 ) 360 )) 361 362 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 363 val immType = SelImm() // used to select imm extractor 364 val common = new ExuInput(exuParams) 365 val addrOH = UInt(iqParams.numEntries.W) 366 367 def exuIdx = exuParams.exuIdx 368 def getSource: SchedulerType = exuParams.getWBSource 369 def getIntWbBusyBundle = common.rfWen.toSeq 370 def getVfWbBusyBundle = common.getVfWen.toSeq 371 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt).toSeq 372 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf).toSeq 373 374 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 375 getIntRfReadBundle.zip(srcType).map { 376 case (rfRd: RfReadPortWithConfig, t: UInt) => 377 makeValid(issueValid && SrcType.isXp(t), rfRd) 378 } 379 } 380 381 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 382 getVfRfReadBundle.zip(srcType).map { 383 case (rfRd: RfReadPortWithConfig, t: UInt) => 384 makeValid(issueValid && SrcType.isVfp(t), rfRd) 385 } 386 } 387 388 def getIntRfWriteValidBundle(issueValid: Bool) = { 389 390 } 391 } 392 393 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 394 val issueQueueParams = this.params 395 val og0resp = Valid(new EntryDeqRespBundle) 396 val og1resp = Valid(new EntryDeqRespBundle) 397 } 398 399 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 400 val respType = RSFeedbackType() // update credit if needs replay 401 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 402 val fuType = FuType() 403 } 404 405 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 406 private val intCertainLat = params.intLatencyCertain 407 private val vfCertainLat = params.vfLatencyCertain 408 private val intLat = params.intLatencyValMax 409 private val vfLat = params.vfLatencyValMax 410 411 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 412 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 413 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 414 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 415 } 416 417 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 418 private val intCertainLat = params.intLatencyCertain 419 private val vfCertainLat = params.vfLatencyCertain 420 private val intLat = params.intLatencyValMax 421 private val vfLat = params.vfLatencyValMax 422 423 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 424 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 425 } 426 427 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 428 private val intCertainLat = params.intLatencyCertain 429 private val vfCertainLat = params.vfLatencyCertain 430 431 val intConflict = OptionWrapper(intCertainLat, Bool()) 432 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 433 } 434 435 // DataPath --[ExuInput]--> Exu 436 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 437 val fuType = FuType() 438 val fuOpType = FuOpType() 439 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 440 val imm = UInt(XLEN.W) 441 val robIdx = new RobPtr 442 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 443 val isFirstIssue = Bool() // Only used by store yet 444 val pdest = UInt(params.wbPregIdxWidth.W) 445 val rfWen = if (params.writeIntRf) Some(Bool()) else None 446 val fpWen = if (params.writeFpRf) Some(Bool()) else None 447 val vecWen = if (params.writeVecRf) Some(Bool()) else None 448 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 449 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 450 val flushPipe = if (params.flushPipe) Some(Bool()) else None 451 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 452 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 453 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 454 Some(new FtqPtr) else None 455 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 456 Some(UInt(log2Up(PredictWidth).W)) else None 457 val predictInfo = if (params.needPdInfo) Some(new Bundle { 458 val target = UInt(VAddrData().dataWidth.W) 459 val taken = Bool() 460 }) else None 461 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 462 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 463 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 464 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 465 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 466 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 467 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 468 val dataSources = Vec(params.numRegSrc, DataSource()) 469 val l1ExuOH = Vec(params.numRegSrc, ExuOH()) 470 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 471 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 472 val deqLdExuIdx = OptionWrapper(params.hasLoadFu || params.hasHyldaFu, UInt(log2Ceil(LoadPipelineWidth).W)) 473 474 val perfDebugInfo = new PerfDebugInfo() 475 476 def exuIdx = this.params.exuIdx 477 478 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 479 if (params.isIQWakeUpSink) { 480 require( 481 og0CancelOH.getWidth == l1ExuOH.head.getWidth, 482 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 483 ) 484 val l1Cancel: Bool = l1ExuOH.zip(srcTimer.get).map { 485 case(exuOH: UInt, srcTimer: UInt) => 486 (exuOH & og0CancelOH).orR && srcTimer === 1.U 487 }.reduce(_ | _) 488 l1Cancel 489 } else { 490 false.B 491 } 492 } 493 494 def getVfWen = { 495 if (params.writeFpRf) this.fpWen 496 else if(params.writeVecRf) this.vecWen 497 else None 498 } 499 500 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 501 // src is assigned to rfReadData 502 this.fuType := source.common.fuType 503 this.fuOpType := source.common.fuOpType 504 this.imm := source.common.imm 505 this.robIdx := source.common.robIdx 506 this.pdest := source.common.pdest 507 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 508 this.iqIdx := source.common.iqIdx // Only used by mem feedback 509 this.dataSources := source.common.dataSources 510 this.l1ExuOH := source.common.l1ExuOH 511 this.rfWen .foreach(_ := source.common.rfWen.get) 512 this.fpWen .foreach(_ := source.common.fpWen.get) 513 this.vecWen .foreach(_ := source.common.vecWen.get) 514 this.fpu .foreach(_ := source.common.fpu.get) 515 this.vpu .foreach(_ := source.common.vpu.get) 516 this.flushPipe .foreach(_ := source.common.flushPipe.get) 517 this.pc .foreach(_ := source.common.pc.get) 518 this.preDecode .foreach(_ := source.common.preDecode.get) 519 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 520 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 521 this.predictInfo .foreach(_ := source.common.predictInfo.get) 522 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 523 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 524 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 525 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 526 this.ssid .foreach(_ := source.common.ssid.get) 527 this.lqIdx .foreach(_ := source.common.lqIdx.get) 528 this.sqIdx .foreach(_ := source.common.sqIdx.get) 529 this.srcTimer .foreach(_ := source.common.srcTimer.get) 530 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 531 this.deqLdExuIdx .foreach(_ := source.common.deqLdExuIdx.get) 532 } 533 } 534 535 // ExuInput --[FuncUnit]--> ExuOutput 536 class ExuOutput( 537 val params: ExeUnitParams, 538 )(implicit 539 val p: Parameters 540 ) extends Bundle with BundleSource with HasXSParameter { 541 val data = UInt(params.dataBitsMax.W) 542 val pdest = UInt(params.wbPregIdxWidth.W) 543 val robIdx = new RobPtr 544 val intWen = if (params.writeIntRf) Some(Bool()) else None 545 val fpWen = if (params.writeFpRf) Some(Bool()) else None 546 val vecWen = if (params.writeVecRf) Some(Bool()) else None 547 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 548 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 549 val wflags = if (params.writeFflags) Some(Bool()) else None 550 val vxsat = if (params.writeVxsat) Some(Bool()) else None 551 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 552 val flushPipe = if (params.flushPipe) Some(Bool()) else None 553 val replay = if (params.replayInst) Some(Bool()) else None 554 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 555 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 556 Some(new SqPtr()) else None 557 val trigger = if (params.trigger) Some(new TriggerCf) else None 558 // uop info 559 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 560 // vldu used only 561 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 562 val vpu = new VPUCtrlSignals 563 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 564 val vdIdx = UInt(3.W) 565 val vdIdxInField = UInt(3.W) 566 val isIndexed = Bool() 567 }) 568 val debug = new DebugBundle 569 val debugInfo = new PerfDebugInfo 570 } 571 572 // ExuOutput + DynInst --> WriteBackBundle 573 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 574 val rfWen = Bool() 575 val fpWen = Bool() 576 val vecWen = Bool() 577 val pdest = UInt(params.pregIdxWidth(backendParams).W) 578 val data = UInt(params.dataWidth.W) 579 val robIdx = new RobPtr()(p) 580 val flushPipe = Bool() 581 val replayInst = Bool() 582 val redirect = ValidIO(new Redirect) 583 val fflags = UInt(5.W) 584 val vxsat = Bool() 585 val exceptionVec = ExceptionVec() 586 val debug = new DebugBundle 587 val debugInfo = new PerfDebugInfo 588 589 this.wakeupSource = s"WB(${params.toString})" 590 591 def fromExuOutput(source: ExuOutput) = { 592 this.rfWen := source.intWen.getOrElse(false.B) 593 this.fpWen := source.fpWen.getOrElse(false.B) 594 this.vecWen := source.vecWen.getOrElse(false.B) 595 this.pdest := source.pdest 596 this.data := source.data 597 this.robIdx := source.robIdx 598 this.flushPipe := source.flushPipe.getOrElse(false.B) 599 this.replayInst := source.replay.getOrElse(false.B) 600 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 601 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 602 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 603 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 604 this.debug := source.debug 605 this.debugInfo := source.debugInfo 606 } 607 608 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 609 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 610 rfWrite.wen := this.rfWen && fire 611 rfWrite.addr := this.pdest 612 rfWrite.data := this.data 613 rfWrite.intWen := this.rfWen 614 rfWrite.fpWen := false.B 615 rfWrite.vecWen := false.B 616 rfWrite 617 } 618 619 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 620 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 621 rfWrite.wen := (this.fpWen || this.vecWen) && fire 622 rfWrite.addr := this.pdest 623 rfWrite.data := this.data 624 rfWrite.intWen := false.B 625 rfWrite.fpWen := this.fpWen 626 rfWrite.vecWen := this.vecWen 627 rfWrite 628 } 629 } 630 631 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 632 // / 633 // [IssueQueue]--> ExuInput -- 634 class ExuBypassBundle( 635 val params: ExeUnitParams, 636 )(implicit 637 val p: Parameters 638 ) extends Bundle { 639 val data = UInt(params.dataBitsMax.W) 640 val pdest = UInt(params.wbPregIdxWidth.W) 641 } 642 643 class ExceptionInfo(implicit p: Parameters) extends Bundle { 644 val pc = UInt(VAddrData().dataWidth.W) 645 val instr = UInt(32.W) 646 val commitType = CommitType() 647 val exceptionVec = ExceptionVec() 648 val singleStep = Bool() 649 val crossPageIPFFix = Bool() 650 val isInterrupt = Bool() 651 val vls = Bool() 652 val trigger = new TriggerCf 653 } 654 655 object UopIdx { 656 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 657 } 658 659 object FuLatency { 660 def apply(): UInt = UInt(width.W) 661 662 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 663 } 664 665 object ExuOH { 666 def apply(exuNum: Int): UInt = UInt(exuNum.W) 667 668 def apply()(implicit p: Parameters): UInt = UInt(width.W) 669 670 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 671 } 672 673 class CancelSignal(implicit p: Parameters) extends XSBundle { 674 val rfWen = Bool() 675 val fpWen = Bool() 676 val vecWen = Bool() 677 val pdest = UInt(PhyRegIdxWidth.W) 678 679 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 680 val pdestMatch = pdest === psrc 681 pdestMatch && ( 682 SrcType.isFp(srcType) && !this.rfWen || 683 SrcType.isXp(srcType) && this.rfWen || 684 SrcType.isVp(srcType) && !this.rfWen 685 ) && valid 686 } 687 } 688 689 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 690 val uop = new DynInst 691 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 692 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 693 val isFirstIssue = Bool() 694 val deqPortIdx = UInt(log2Ceil(LoadPipelineWidth).W) 695 696 def src_rs1 = src(0) 697 def src_stride = src(1) 698 def src_vs3 = src(2) 699 def src_mask = if (isVector) src(3) else 0.U 700 def src_vl = if (isVector) src(4) else 0.U 701 } 702 703 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 704 val uop = new DynInst 705 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 706 val mask = if (isVector) Some(UInt(VLEN.W)) else None 707 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 708 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 709 val debug = new DebugBundle 710 711 def isVls = FuType.isVls(uop.fuType) 712 } 713 714 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 715 val uop = new DynInst 716 val flag = UInt(1.W) 717 } 718 719 object LoadShouldCancel { 720 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 721 val ld1Cancel = loadDependency.map(deps => 722 deps.zipWithIndex.map { case (dep, ldPortIdx) => 723 ldCancel.map(_.ld1Cancel).map(cancel => cancel.fire && dep(1) && cancel.bits === ldPortIdx.U).reduce(_ || _) 724 }.reduce(_ || _) 725 ) 726 val ld2Cancel = loadDependency.map(deps => 727 deps.zipWithIndex.map { case (dep, ldPortIdx) => 728 ldCancel.map(_.ld2Cancel).map(cancel => cancel.fire && dep(2) && cancel.bits === ldPortIdx.U).reduce(_ || _) 729 }.reduce(_ || _) 730 ) 731 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 732 } 733 } 734} 735