1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 val IQValidNumVec = Output(MixedVec(backendParams.genIQValidNumBundle)) 53 54 val fromCtrlBlock = new Bundle { 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuOH(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuOH(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 val vecLoadIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.VlduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 88 89 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 90 91 val memIO = if (params.isMemSchd) Some(new Bundle { 92 val lsqEnqIO = Flipped(new LsqEnqIO) 93 }) else None 94 val fromMem = if (params.isMemSchd) Some(new Bundle { 95 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 96 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 97 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 98 val vstuFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 99 val vlduFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 100 val stIssuePtr = Input(new SqPtr()) 101 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 102 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 103 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 104 val lqDeqPtr = Input(new LqPtr) 105 val sqDeqPtr = Input(new SqPtr) 106 // from lsq 107 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 108 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 109 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 110 }) else None 111 val toMem = if (params.isMemSchd) Some(new Bundle { 112 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 113 }) else None 114} 115 116abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 117 extends LazyModuleImp(wrapper) 118 with HasXSParameter 119{ 120 val io = IO(new SchedulerIO()) 121 122 // alias 123 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 124 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 125 private val schdType = params.schdType 126 127 // Modules 128 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 129 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 130 if (params.isIntSchd) { 131 dispatch2Iq.io.IQValidNumVec.get := io.IQValidNumVec 132 io.IQValidNumVec := MixedVecInit(issueQueues.map(_.io.validCntDeqVec)) 133 } 134 else io.IQValidNumVec := 0.U.asTypeOf(io.IQValidNumVec) 135 136 // valid count 137 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 138 139 // BusyTable Modules 140 val intBusyTable = schdType match { 141 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 142 case _ => None 143 } 144 145 val vfBusyTable = schdType match { 146 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 147 case _ => None 148 } 149 150 dispatch2Iq.io match { case dp2iq => 151 dp2iq.redirect <> io.fromCtrlBlock.flush 152 dp2iq.in <> io.fromDispatch.uops 153 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 154 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 155 } 156 157 intBusyTable match { 158 case Some(bt) => 159 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 160 btAllocPregs.valid := dpAllocPregs.isInt 161 btAllocPregs.bits := dpAllocPregs.preg 162 } 163 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 164 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 165 wb.bits := io.intWriteBack(i).addr 166 } 167 bt.io.wakeUp := io.fromSchedulers.wakeupVec 168 bt.io.cancel := io.fromDataPath.cancelToBusyTable 169 bt.io.ldCancel := io.ldCancel 170 case None => 171 } 172 173 vfBusyTable match { 174 case Some(bt) => 175 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 176 btAllocPregs.valid := dpAllocPregs.isFp 177 btAllocPregs.bits := dpAllocPregs.preg 178 } 179 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 180 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 181 wb.bits := io.vfWriteBack(i).addr 182 } 183 bt.io.wakeUp := io.fromSchedulers.wakeupVec 184 bt.io.cancel := io.fromDataPath.cancelToBusyTable 185 bt.io.ldCancel := io.ldCancel 186 case None => 187 } 188 189 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 190 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 191 192 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 193 sink.valid := source.wen 194 sink.bits.rfWen := source.intWen 195 sink.bits.fpWen := source.fpWen 196 sink.bits.vecWen := source.vecWen 197 sink.bits.pdest := source.addr 198 } 199 200 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 201 sink.valid := source.wen 202 sink.bits.rfWen := source.intWen 203 sink.bits.fpWen := source.fpWen 204 sink.bits.vecWen := source.vecWen 205 sink.bits.pdest := source.addr 206 } 207 208 // Connect bundles having the same wakeup source 209 issueQueues.zipWithIndex.foreach { case(iq, i) => 210 iq.io.wakeupFromIQ.foreach { wakeUp => 211 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 212 val exuIdx = wakeUp.bits.exuIdx 213 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 214 connectSamePort(wakeUp,wakeUpIn) 215 backendParams.connectWakeup(exuIdx) 216 if (backendParams.isCopyPdest(exuIdx)) { 217 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 218 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 219 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 220 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 221 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 222 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 223 } 224 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 225 if (iq.params.numVfSrc == 0) wakeUp.bits.fpWen := false.B 226 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 227 } 228 iq.io.og0Cancel := io.fromDataPath.og0Cancel 229 iq.io.og1Cancel := io.fromDataPath.og1Cancel 230 iq.io.ldCancel := io.ldCancel 231 } 232 233 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 234 issueQueues.flatMap(_.io.wakeupToIQ) 235 .map(x => (x.bits.exuIdx, x)) 236 .toMap 237 238 // Connect bundles having the same wakeup source 239 io.toSchedulers.wakeupVec.foreach { wakeUp => 240 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 241 } 242 243 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 244 toDpDy <> issueQueues(i).io.deqDelay 245 } 246 247 // Response 248 issueQueues.zipWithIndex.foreach { case (iq, i) => 249 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 250 og0Resp := io.fromDataPath(i)(j).og0resp 251 } 252 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 253 og1Resp := io.fromDataPath(i)(j).og1resp 254 } 255 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 256 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 257 finalIssueResp := io.loadFinalIssueResp(i)(j) 258 } else { 259 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 260 } 261 }) 262 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 263 if (io.memAddrIssueResp(i).isDefinedAt(j)) { 264 memAddrIssueResp := io.memAddrIssueResp(i)(j) 265 } else { 266 memAddrIssueResp := 0.U.asTypeOf(memAddrIssueResp) 267 } 268 }) 269 iq.io.vecLoadIssueResp.foreach(_.zipWithIndex.foreach { case (resp, deqIdx) => 270 resp := io.vecLoadIssueResp(i)(deqIdx) 271 }) 272 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 273 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 274 } 275 276 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 277 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 278 279 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 280 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 281} 282 283class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 284 extends SchedulerImpBase(wrapper) 285 with HasXSParameter 286{ 287// dontTouch(io.vfWbFuBusyTable) 288 println(s"[SchedulerArithImp] " + 289 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 290 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 291 292 issueQueues.zipWithIndex.foreach { case (iq, i) => 293 iq.io.flush <> io.fromCtrlBlock.flush 294 iq.io.enq <> dispatch2Iq.io.out(i) 295 val intWBIQ = params.schdType match { 296 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 297 case VfScheduler() => wakeupFromVfWBVec 298 case _ => null 299 } 300 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 301 } 302} 303 304// FIXME: Vector mem instructions may not be handled properly! 305class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 306 extends SchedulerImpBase(wrapper) 307 with HasXSParameter 308{ 309 println(s"[SchedulerMemImp] " + 310 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 311 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 312 313 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 314 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 315 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 316 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 317 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 318 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 319 320 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 321 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 322 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 323 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 324 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 325 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 326 327 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 328 329 private val loadWakeUp = issueQueues.filter(_.params.LdExuCnt > 0).map(_.asInstanceOf[IssueQueueMemAddrImp].io.memIO.get.loadWakeUp).flatten 330 require(loadWakeUp.length == io.fromMem.get.wakeup.length) 331 loadWakeUp.zip(io.fromMem.get.wakeup).foreach(x => x._1 := x._2) 332 333 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 334 iq.io.flush <> io.fromCtrlBlock.flush 335 iq.io.enq <> dispatch2Iq.io.out(i) 336 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 337 } 338 339 ldAddrIQs.zipWithIndex.foreach { 340 case (imp: IssueQueueMemAddrImp, i) => 341 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 342 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 343 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 344 case _ => 345 } 346 347 stAddrIQs.zipWithIndex.foreach { 348 case (imp: IssueQueueMemAddrImp, i) => 349 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 350 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 351 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 352 case _ => 353 } 354 355 hyuIQs.zip(hyuIQIdxs).foreach { 356 case (imp: IssueQueueMemAddrImp, idx) => 357 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 358 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 359 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 360 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 361 // TODO: refactor ditry code 362 imp.io.deqDelay(1).ready := false.B 363 io.toDataPathAfterDelay(idx)(1).valid := false.B 364 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 365 case _ => 366 } 367 368 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 369 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 370 371 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 372 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 373 374 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 375 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 376 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 377 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 378 379 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 380 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 381 382 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 383 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 384 385 val d2IqStaOut = dispatch2Iq.io.out.zipWithIndex.filter(staIdxSeq contains _._2).unzip._1.flatten 386 d2IqStaOut.zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 387 val isAllReady = staIQ.ready && stdIQ.ready 388 dp.ready := isAllReady 389 staIQ.valid := dp.valid && isAllReady 390 stdIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 391 } 392 393 val d2IqHyaOut = dispatch2Iq.io.out.zipWithIndex.filter(hyaIdxSeq contains _._2).unzip._1.flatten 394 d2IqHyaOut.zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 395 val isAllReady = hyaIQ.ready && hydIQ.ready 396 dp.ready := isAllReady 397 hyaIQ.valid := dp.valid && isAllReady 398 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 399 } 400 401 stDataIQs.zipWithIndex.foreach { case (iq, i) => 402 iq.io.flush <> io.fromCtrlBlock.flush 403 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 404 } 405 406 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 407 stdIQEnq.bits := staIQEnq.bits 408 // Store data reuses store addr src(1) in dispatch2iq 409 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 410 // \ 411 // ---src*(1)--> [stdIQ] 412 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 413 // instead of dispatch2Iq.io.out(x).bits.src*(1) 414 val stdIdx = 1 415 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 416 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 417 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 418 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 419 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 420 } 421 422 vecMemIQs.foreach { 423 case imp: IssueQueueVecMemImp => 424 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 425 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 426 // not used 427 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.vstuFeedback.head // only vector store replay 428 // maybe not used 429 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 430 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 431 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 432 433 case _ => 434 } 435 436 val lsqEnqCtrl = Module(new LsqEnqCtrl) 437 438 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 439 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 440 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 441 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 442 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 443 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 444 dispatch2Iq.io.lqFreeCount.get := lsqEnqCtrl.io.lqFreeCount 445 dispatch2Iq.io.sqFreeCount.get := lsqEnqCtrl.io.sqFreeCount 446 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 447 448 dontTouch(io.vecLoadIssueResp) 449} 450