1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => log2Up(n) 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 p => p.copy( 66 DecodeWidth = 6, 67 RenameWidth = 6, 68 RobCommitWidth = 8, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 24, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 // ============ VLSU ============ 81 VlMergeBufferSize = 8, 82 VsMergeBufferSize = 8, 83 UopWritebackWidth = 1, 84 SplitBufferSize = 8, 85 // ============================== 86 RobSize = 48, 87 RabSize = 96, 88 FtqSize = 8, 89 IBufSize = 24, 90 IBufNBank = 6, 91 StoreBufferSize = 4, 92 StoreBufferThreshold = 3, 93 IssueQueueSize = 8, 94 IssueQueueCompEntrySize = 4, 95 dpParams = DispatchParameters( 96 IntDqSize = 12, 97 FpDqSize = 12, 98 LsDqSize = 12, 99 IntDqDeqWidth = 8, 100 FpDqDeqWidth = 4, 101 LsDqDeqWidth = 6 102 ), 103 intPreg = IntPregParams( 104 numEntries = 64, 105 numRead = None, 106 numWrite = None, 107 ), 108 vfPreg = VfPregParams( 109 numEntries = 160, 110 numRead = None, 111 numWrite = None, 112 ), 113 icacheParameters = ICacheParameters( 114 nSets = 64, // 16KB ICache 115 tagECC = Some("parity"), 116 dataECC = Some("parity"), 117 replacer = Some("setplru"), 118 nMissEntries = 2, 119 nReleaseEntries = 1, 120 nProbeEntries = 2, 121 // fdip 122 enableICachePrefetch = true, 123 prefetchToL1 = false, 124 ), 125 dcacheParametersOpt = Some(DCacheParameters( 126 nSets = 64, // 32KB DCache 127 nWays = 8, 128 tagECC = Some("secded"), 129 dataECC = Some("secded"), 130 replacer = Some("setplru"), 131 nMissEntries = 4, 132 nProbeEntries = 4, 133 nReleaseEntries = 8, 134 nMaxPrefetchEntry = 2, 135 )), 136 EnableBPD = false, // disable TAGE 137 EnableLoop = false, 138 itlbParameters = TLBParameters( 139 name = "itlb", 140 fetchi = true, 141 useDmode = false, 142 NWays = 4, 143 ), 144 ldtlbParameters = TLBParameters( 145 name = "ldtlb", 146 NWays = 4, 147 partialStaticPMP = true, 148 outsideRecvFlush = true, 149 outReplace = false, 150 lgMaxSize = 4 151 ), 152 sttlbParameters = TLBParameters( 153 name = "sttlb", 154 NWays = 4, 155 partialStaticPMP = true, 156 outsideRecvFlush = true, 157 outReplace = false, 158 lgMaxSize = 4 159 ), 160 hytlbParameters = TLBParameters( 161 name = "hytlb", 162 NWays = 4, 163 partialStaticPMP = true, 164 outsideRecvFlush = true, 165 outReplace = false, 166 lgMaxSize = 4 167 ), 168 pftlbParameters = TLBParameters( 169 name = "pftlb", 170 NWays = 4, 171 partialStaticPMP = true, 172 outsideRecvFlush = true, 173 outReplace = false, 174 lgMaxSize = 4 175 ), 176 btlbParameters = TLBParameters( 177 name = "btlb", 178 NWays = 4, 179 ), 180 l2tlbParameters = L2TLBParameters( 181 l1Size = 4, 182 l2nSets = 4, 183 l2nWays = 4, 184 l3nSets = 4, 185 l3nWays = 8, 186 spSize = 2, 187 ), 188 L2CacheParamsOpt = Some(L2Param( 189 name = "L2", 190 ways = 8, 191 sets = 128, 192 echoField = Seq(huancun.DirtyField()), 193 prefetch = None, 194 clientCaches = Seq(L1Param( 195 "dcache", 196 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 197 )), 198 ) 199 ), 200 L2NBanks = 2, 201 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 202 ) 203 ) 204 case SoCParamsKey => 205 val tiles = site(XSTileKey) 206 up(SoCParamsKey).copy( 207 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 208 sets = 1024, 209 inclusive = false, 210 clientCaches = tiles.map{ core => 211 val clientDirBytes = tiles.map{ t => 212 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 213 }.sum 214 val l2params = core.L2CacheParamsOpt.get.toCacheParams 215 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 216 }, 217 simulation = !site(DebugOptionsKey).FPGAPlatform, 218 prefetch = None 219 )), 220 L3NBanks = 1 221 ) 222 }) 223) 224 225// Non-synthesizable MinimalConfig, for fast simulation only 226class MinimalSimConfig(n: Int = 1) extends Config( 227 new MinimalConfig(n).alter((site, here, up) => { 228 case XSTileKey => up(XSTileKey).map(_.copy( 229 dcacheParametersOpt = None, 230 softPTW = true 231 )) 232 case SoCParamsKey => up(SoCParamsKey).copy( 233 L3CacheParamsOpt = None 234 ) 235 }) 236) 237 238class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 239 case XSTileKey => 240 val sets = n * 1024 / ways / 64 241 up(XSTileKey).map(_.copy( 242 dcacheParametersOpt = Some(DCacheParameters( 243 nSets = sets, 244 nWays = ways, 245 tagECC = Some("secded"), 246 dataECC = Some("secded"), 247 replacer = Some("setplru"), 248 nMissEntries = 16, 249 nProbeEntries = 8, 250 nReleaseEntries = 18, 251 nMaxPrefetchEntry = 6, 252 )) 253 )) 254}) 255 256class WithNKBL2 257( 258 n: Int, 259 ways: Int = 8, 260 inclusive: Boolean = true, 261 banks: Int = 1 262) extends Config((site, here, up) => { 263 case XSTileKey => 264 require(inclusive, "L2 must be inclusive") 265 val upParams = up(XSTileKey) 266 val l2sets = n * 1024 / banks / ways / 64 267 upParams.map(p => p.copy( 268 L2CacheParamsOpt = Some(L2Param( 269 name = "L2", 270 ways = ways, 271 sets = l2sets, 272 clientCaches = Seq(L1Param( 273 "dcache", 274 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 275 ways = p.dcacheParametersOpt.get.nWays + 2, 276 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 277 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 278 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 279 )), 280 reqField = Seq(utility.ReqSourceField()), 281 echoField = Seq(huancun.DirtyField()), 282 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 283 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 284 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 285 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 286 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 287 )), 288 L2NBanks = banks 289 )) 290}) 291 292class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 293 case SoCParamsKey => 294 val sets = n * 1024 / banks / ways / 64 295 val tiles = site(XSTileKey) 296 val clientDirBytes = tiles.map{ t => 297 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 298 }.sum 299 up(SoCParamsKey).copy( 300 L3NBanks = banks, 301 L3CacheParamsOpt = Some(HCCacheParameters( 302 name = "L3", 303 level = 3, 304 ways = ways, 305 sets = sets, 306 inclusive = inclusive, 307 clientCaches = tiles.map{ core => 308 val l2params = core.L2CacheParamsOpt.get.toCacheParams 309 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 310 }, 311 enablePerf = true, 312 ctrl = Some(CacheCtrl( 313 address = 0x39000000, 314 numCores = tiles.size 315 )), 316 reqField = Seq(utility.ReqSourceField()), 317 sramClkDivBy2 = true, 318 sramDepthDiv = 4, 319 tagECC = Some("secded"), 320 dataECC = Some("secded"), 321 simulation = !site(DebugOptionsKey).FPGAPlatform, 322 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 323 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 324 )) 325 ) 326}) 327 328class WithL3DebugConfig extends Config( 329 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 330) 331 332class MinimalL3DebugConfig(n: Int = 1) extends Config( 333 new WithL3DebugConfig ++ new MinimalConfig(n) 334) 335 336class DefaultL3DebugConfig(n: Int = 1) extends Config( 337 new WithL3DebugConfig ++ new BaseConfig(n) 338) 339 340class WithFuzzer extends Config((site, here, up) => { 341 case DebugOptionsKey => up(DebugOptionsKey).copy( 342 EnablePerfDebug = false, 343 ) 344 case SoCParamsKey => up(SoCParamsKey).copy( 345 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 346 enablePerf = false, 347 )), 348 ) 349 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 350 p.copy( 351 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 352 enablePerf = false, 353 )), 354 ) 355 } 356}) 357 358class MinimalAliasDebugConfig(n: Int = 1) extends Config( 359 new WithNKBL3(512, inclusive = false) ++ 360 new WithNKBL2(256, inclusive = true) ++ 361 new WithNKBL1D(128) ++ 362 new MinimalConfig(n) 363) 364 365class MediumConfig(n: Int = 1) extends Config( 366 new WithNKBL3(4096, inclusive = false, banks = 4) 367 ++ new WithNKBL2(512, inclusive = true) 368 ++ new WithNKBL1D(128) 369 ++ new BaseConfig(n) 370) 371 372class FuzzConfig(dummy: Int = 0) extends Config( 373 new WithFuzzer 374 ++ new DefaultConfig(1) 375) 376 377class DefaultConfig(n: Int = 1) extends Config( 378 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 379 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 380 ++ new WithNKBL1D(64, ways = 4) 381 ++ new BaseConfig(n) 382) 383