xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala (revision 01cdded87283f55be427ca849d18baa3e9459c2d) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL}
5import xiangshan.backend.fu.NewCSR.CSRFunc._
6import xiangshan.backend.fu.vector.Bundles._
7import xiangshan.backend.fu.NewCSR.CSRConfig._
8import xiangshan.backend.fu.fpu.Bundles.{Fflags, Frm}
9import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
10
11import scala.collection.immutable.SeqMap
12
13trait Unprivileged { self: NewCSR with MachineLevel with SupervisorLevel =>
14
15  val fcsr = Module(new CSRModule("Fcsr", new CSRBundle {
16    val NX = WARL(0, wNoFilter)
17    val UF = WARL(1, wNoFilter)
18    val OF = WARL(2, wNoFilter)
19    val DZ = WARL(3, wNoFilter)
20    val NV = WARL(4, wNoFilter)
21    val FRM = WARL(7, 5, wNoFilter)
22  }) with HasRobCommitBundle {
23    val wAliasFflags = IO(Input(new CSRAddrWriteBundle(new CSRFFlagsBundle)))
24    val wAliasFfm = IO(Input(new CSRAddrWriteBundle(new CSRFrmBundle)))
25    val fflags = IO(Output(Fflags()))
26    val frm = IO(Output(Frm()))
27
28    // write connection
29    this.wfn(reg)(Seq(wAliasFflags, wAliasFfm))
30
31    when (robCommit.fflags.valid) {
32      reg.NX := robCommit.fflags.bits(0) || reg.NX
33      reg.UF := robCommit.fflags.bits(1) || reg.UF
34      reg.OF := robCommit.fflags.bits(2) || reg.OF
35      reg.DZ := robCommit.fflags.bits(3) || reg.DZ
36      reg.NV := robCommit.fflags.bits(4) || reg.NV
37    }
38
39    // read connection
40    fflags := reg.asUInt(4, 0)
41    frm := reg.FRM.asUInt
42  }).setAddr(0x003)
43
44  // vec
45  val vstart = Module(new CSRModule("Vstart", new CSRBundle {
46    val vstart = RW(VlWidth - 2, 0) // hold [0, 128)
47  }) with HasRobCommitBundle {
48    // Todo make The use of vstart values greater than the largest element index for the current SEW setting is reserved.
49    // Not trap
50    when (wen && this.w.wdata < VLEN.U) {
51      reg.vstart := this.w.wdata(VlWidth - 2, 0)
52    }.elsewhen (robCommit.vstart.valid) {
53      reg.vstart := robCommit.vstart.bits
54    }
55  })
56    .setAddr(0x008)
57
58  val vcsr = Module(new CSRModule("Vcsr", new CSRBundle {
59    val VXSAT = RW(   0)
60    val VXRM  = RW(2, 1)
61  }) with HasRobCommitBundle {
62    val wAliasVxsat = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
63      val VXSAT = RW(0)
64    })))
65    val wAlisaVxrm = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
66      val VXRM = RW(1, 0)
67    })))
68    val vxsat = IO(Output(Vxsat()))
69    val vxrm  = IO(Output(Vxrm()))
70
71    // write connection
72    this.wfn(reg)(Seq(wAliasVxsat, wAlisaVxrm))
73
74    when(robCommit.vxsat.valid) {
75      reg.VXSAT := reg.VXSAT.asBool || robCommit.vxsat.bits.asBool
76    }
77
78    // read connection
79    vxsat := reg.VXSAT.asUInt
80    vxrm  := reg.VXRM.asUInt
81  }).setAddr(0x00F)
82
83  val vl = Module(new CSRModule("Vl", new CSRBundle {
84    val VL = RO(VlWidth - 1, 0)
85  }) with HasRobCommitBundle {
86    when (robCommit.vl.valid) {
87      reg.VL := robCommit.vl.bits
88    }
89  })
90    .setAddr(0xC20)
91
92  val vtype = Module(new CSRModule("Vtype", new CSRVTypeBundle) with HasRobCommitBundle {
93    when(robCommit.vtype.valid) {
94      reg := robCommit.vtype.bits
95    }
96  })
97    .setAddr(0xC21)
98
99  val vlenb = Module(new CSRModule("Vlenb", new CSRBundle {
100    val VLENB = VlenbField(63, 0).withReset(VlenbField.init)
101  }))
102    .setAddr(0xC22)
103
104  val unprivilegedCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], Data)] = SeqMap(
105    0x001 -> (fcsr.wAliasFflags -> fcsr.fflags),
106    0x002 -> (fcsr.wAliasFfm    -> fcsr.frm),
107    0x003 -> (fcsr.w            -> fcsr.rdata),
108    0x008 -> (vstart.w          -> vstart.rdata),
109    0x009 -> (vcsr.wAliasVxsat  -> vcsr.vxsat),
110    0x00A -> (vcsr.wAlisaVxrm   -> vcsr.vxrm),
111    0x00F -> (vcsr.w            -> vcsr.rdata),
112    0xC20 -> (vl.w              -> vl.rdata),
113    0xC21 -> (vtype.w           -> vtype.rdata),
114    0xC22 -> (vlenb.w           -> vlenb.rdata),
115  )
116
117  val unprivilegedCSRMods: Seq[CSRModule[_]] = Seq(
118    fcsr,
119    vcsr,
120    vstart,
121    vl,
122    vtype,
123    vlenb,
124  )
125
126  val unprivilegedCSROutMap: SeqMap[Int, UInt] = SeqMap(
127    0x001 -> fcsr.fflags.asUInt,
128    0x002 -> fcsr.frm.asUInt,
129    0x003 -> fcsr.rdata.asUInt,
130    0x008 -> vcsr.rdata.asUInt,
131    0x009 -> vcsr.vxsat.asUInt,
132    0x00A -> vcsr.vxrm.asUInt,
133    0x00F -> vcsr.rdata.asUInt,
134    0xC20 -> vl.rdata.asUInt,
135    0xC21 -> vtype.rdata.asUInt,
136    0xC22 -> vlenb.rdata.asUInt,
137  )
138}
139
140class CSRVTypeBundle extends CSRBundle {
141  val VILL  = RO(  63)
142  val VMA   = RO(   7)
143  val VTA   = RO(   6)
144  val VSEW  = RO(5, 3)
145  val VLMUL = RO(2, 0)
146}
147
148class CSRFrmBundle extends CSRBundle {
149  val FRM = WARL(2, 0, wNoFilter)
150}
151
152class CSRFFlagsBundle extends CSRBundle {
153  val NX = WARL(0, wNoFilter)
154  val UF = WARL(1, wNoFilter)
155  val OF = WARL(2, wNoFilter)
156  val DZ = WARL(3, wNoFilter)
157  val NV = WARL(4, wNoFilter)
158}
159
160object VlenbField extends CSREnum with ROApply {
161  val init = Value((VLEN / 8).U)
162}
163