style(csr): fix typo in CSR (#4310)

fix(Unprivileged): wait a cycle to update `time` when `nextV =/= v` (#4132)

fix(csr): update time reg when virtual mode changes (#4111)

* Since we only implement one time register to hold the value of
`time`(used in non-virtual mode) and `time + htimedelta`(used in virtual

fix(csr): update time reg when virtual mode changes (#4111)

* Since we only implement one time register to hold the value of
`time`(used in non-virtual mode) and `time + htimedelta`(used in virtual
mode), the value should be updated when virtual mode changes.
* Otherwise, when virtual mode changes and rtc clock tick does not
assert, the value in `time` register does not match the current virtual
mode.

Co-authored-by: Xuan Hu <[email protected]>

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fix(CSR): fix dcsr to support stopcount & stoptime

fix(CSR): Add legalization code for mstatus.MPP, mnstatus.MNPP and dcsr.PRV (#3577)

csr: execute inst will raise EX_II when rm is reserved value.

* When 0 <= inst.rm <= 4, execute inst as usual.
* When inst.rm = 5/6, execute inst will raise EX_II.
* When inst.rm = 7, rm

csr: execute inst will raise EX_II when rm is reserved value.

* When 0 <= inst.rm <= 4, execute inst as usual.
* When inst.rm = 5/6, execute inst will raise EX_II.
* When inst.rm = 7, rm = frm.data. if frm.data > 4 will raise EX_II.

* Meanwhile, flush pipe when
* 1. wen frm CSR and wdata > 4
* 2. wen fcsr CSR and wdata(7, 5) > 4
* 3. wen frm/fcsr CSR and frm.rdata is reserved

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CSR: initialize vstart to avoid X propagation at DecodeStage

vtype: init vtype's vill to 1 and other fields to 0

NewCSR: write bit of [6:0] for vstart CSR when wdata >= VLEN (#3249)

NewCSR: set legal init value to WARL Field

NewCSR: set vstart to zero when setting VS dirty

tmp-NewCSR: fix connection of CSR vector bundles

NewCSR: use rocketchip's CSR addr

NewCSR: fix rdata when VS mode access VS CSRs by address of S mode

NewCSR: use rocketchip's CSR addr

NewCSR: connected perfevent to newcsr

NewCSR: update time CSR

* Read time CSR in VS or VU mode return htimedelta + actual value of time
* Add stime, vstime output IO to saving adder

NewCSR: support Sstc extension

* Add `stimecmp` and `vstimecmp` CSR.
* Add `STIP` and `VSTIP` interrupt.
* Add `STCE` field in `menvcfg` and `henvcfg` to enable Sstc extension.

NewCSR: add `cycle` and `instret` support

NewCSR: add time CSR support

NewCSR: fix unprivileged CSRs and permission check

* Add commit vstart
* Fix commit connection
* Fix permission check
* Fix mstatus.VS/FS initial with off
* Add fp/vec.off bundle to decode
* Flush w

NewCSR: fix unprivileged CSRs and permission check

* Add commit vstart
* Fix commit connection
* Fix permission check
* Fix mstatus.VS/FS initial with off
* Add fp/vec.off bundle to decode
* Flush when change vxrm
* Add more skip condition for mip and hip

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NewCSR: add IMSIC

NewCSR: add fu wrapper

NewCSR: modulized implementation

NewCSR: add Hypervisor CSRs

NewCSR: optimize dump fields using chisel3.reflect.DataMirror

NewCSR: add VirtualSupervisor CSRs

NewCSR: refactor VirtualSupervisor an

NewCSR: modulized implementation

NewCSR: add Hypervisor CSRs

NewCSR: optimize dump fields using chisel3.reflect.DataMirror

NewCSR: add VirtualSupervisor CSRs

NewCSR: refactor VirtualSupervisor and Hypervisor CSRs

* Make sure ValidIO etc function return CSREnumType not EnumType
* TODO: AIA for vs

NewCSR: add MachineLevel CSRs

NewCSR: fix alias relationship between hip, hvip and vsip

NewCSR: add SupervisorLevel CSRs

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