xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala (revision d23963a8a6d513ce795bf3f96352718fa39434b7) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import freechips.rocketchip.rocket.CSRs
6import utility.GatedValidRegNext
7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL}
8import xiangshan.backend.fu.NewCSR.CSRFunc._
9import xiangshan.backend.fu.vector.Bundles._
10import xiangshan.backend.fu.NewCSR.CSRConfig._
11import xiangshan.backend.fu.fpu.Bundles.{Fflags, Frm}
12import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
13
14import scala.collection.immutable.SeqMap
15
16trait Unprivileged { self: NewCSR with MachineLevel with SupervisorLevel =>
17
18  val fcsr = Module(new CSRModule("Fcsr", new CSRBundle {
19    val NX = WARL(0, wNoFilter)
20    val UF = WARL(1, wNoFilter)
21    val OF = WARL(2, wNoFilter)
22    val DZ = WARL(3, wNoFilter)
23    val NV = WARL(4, wNoFilter)
24    val FRM = WARL(7, 5, wNoFilter)
25  }) with HasRobCommitBundle {
26    val wAliasFflags = IO(Input(new CSRAddrWriteBundle(new CSRFFlagsBundle)))
27    val wAliasFfm = IO(Input(new CSRAddrWriteBundle(new CSRFrmBundle)))
28    val fflags = IO(Output(Fflags()))
29    val frm = IO(Output(Frm()))
30    val fflagsRdata = IO(Output(Fflags()))
31    val frmRdata = IO(Output(Frm()))
32
33    // write connection
34    this.wfn(reg)(Seq(wAliasFflags, wAliasFfm))
35
36    when (robCommit.fflags.valid) {
37      reg.NX := robCommit.fflags.bits(0) || reg.NX
38      reg.UF := robCommit.fflags.bits(1) || reg.UF
39      reg.OF := robCommit.fflags.bits(2) || reg.OF
40      reg.DZ := robCommit.fflags.bits(3) || reg.DZ
41      reg.NV := robCommit.fflags.bits(4) || reg.NV
42    }
43
44    // read connection
45    fflags := reg.asUInt(4, 0)
46    frm := reg.FRM.asUInt
47
48    fflagsRdata := fflags.asUInt
49    frmRdata := frm.asUInt
50  }).setAddr(CSRs.fcsr)
51
52  // vec
53  val vstart = Module(new CSRModule("Vstart", new CSRBundle {
54    val vstart = RW(VlWidth - 2, 0) // hold [0, 128)
55  }) with HasRobCommitBundle {
56    // Todo make The use of vstart values greater than the largest element index for the current SEW setting is reserved.
57    // Not trap
58    when (wen && this.w.wdata < VLEN.U) {
59      reg.vstart := this.w.wdata(VlWidth - 2, 0)
60    }.elsewhen (robCommit.vstart.valid) {
61      reg.vstart := robCommit.vstart.bits
62    }
63  })
64    .setAddr(CSRs.vstart)
65
66  val vcsr = Module(new CSRModule("Vcsr", new CSRBundle {
67    val VXSAT = RW(   0)
68    val VXRM  = RW(2, 1)
69  }) with HasRobCommitBundle {
70    val wAliasVxsat = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
71      val VXSAT = RW(0)
72    })))
73    val wAlisaVxrm = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
74      val VXRM = RW(1, 0)
75    })))
76    val vxsat = IO(Output(Vxsat()))
77    val vxrm  = IO(Output(Vxrm()))
78
79    // write connection
80    this.wfn(reg)(Seq(wAliasVxsat, wAlisaVxrm))
81
82    when(robCommit.vxsat.valid) {
83      reg.VXSAT := reg.VXSAT.asBool || robCommit.vxsat.bits.asBool
84    }
85
86    // read connection
87    vxsat := reg.VXSAT.asUInt
88    vxrm  := reg.VXRM.asUInt
89  }).setAddr(CSRs.vcsr)
90
91  val vl = Module(new CSRModule("Vl", new CSRBundle {
92    val VL = RO(VlWidth - 1, 0)
93  }))
94    .setAddr(CSRs.vl)
95
96  val vtype = Module(new CSRModule("Vtype", new CSRVTypeBundle) with HasRobCommitBundle {
97    when(robCommit.vtype.valid) {
98      reg := robCommit.vtype.bits
99    }
100  })
101    .setAddr(CSRs.vtype)
102
103  val vlenb = Module(new CSRModule("Vlenb", new CSRBundle {
104    val VLENB = VlenbField(63, 0).withReset(VlenbField.init)
105  }))
106    .setAddr(CSRs.vlenb)
107
108  val cycle = Module(new CSRModule("cycle", new CSRBundle {
109    val cycle = RO(63, 0)
110  }) with HasMHPMSink {
111    regOut.cycle := mHPM.cycle
112  })
113    .setAddr(CSRs.cycle)
114
115  val time = Module(new CSRModule("time", new CSRBundle {
116    val time = RO(63, 0)
117  }) with HasMHPMSink {
118    val updated = IO(Output(Bool()))
119    val stime  = IO(Output(UInt(64.W)))
120    val vstime = IO(Output(UInt(64.W)))
121
122    val stimeTmp  = mHPM.time.bits
123    val vstimeTmp = mHPM.time.bits + htimedelta
124
125    when (mHPM.time.valid) {
126      reg.time := Mux(v, vstimeTmp, stimeTmp)
127    }
128
129    updated := GatedValidRegNext(mHPM.time.valid)
130    stime  := stimeTmp
131    vstime := vstimeTmp
132  })
133    .setAddr(CSRs.time)
134
135  val instret = Module(new CSRModule("instret", new CSRBundle {
136    val instret = RO(63, 0)
137  }) with HasMHPMSink {
138    regOut.instret := mHPM.instret
139  })
140    .setAddr(CSRs.instret)
141
142  val hpmcounters: Seq[CSRModule[_]] = (3 to 0x1F).map(num =>
143    Module(new CSRModule(s"Hpmcounter$num", new CSRBundle {
144      val hpmcounter = RO(63, 0)
145    }) with HasMHPMSink {
146      regOut.hpmcounter := mHPM.hpmcounters(num - 3)
147    }).setAddr(CSRs.cycle + num)
148  )
149
150  val unprivilegedCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] = SeqMap(
151    CSRs.fflags -> (fcsr.wAliasFflags -> fcsr.fflagsRdata),
152    CSRs.frm    -> (fcsr.wAliasFfm    -> fcsr.frmRdata),
153    CSRs.fcsr   -> (fcsr.w            -> fcsr.rdata),
154    CSRs.vstart -> (vstart.w          -> vstart.rdata),
155    CSRs.vxsat  -> (vcsr.wAliasVxsat  -> vcsr.vxsat),
156    CSRs.vxrm   -> (vcsr.wAlisaVxrm   -> vcsr.vxrm),
157    CSRs.vcsr   -> (vcsr.w            -> vcsr.rdata),
158    CSRs.vl     -> (vl.w              -> vl.rdata),
159    CSRs.vtype  -> (vtype.w           -> vtype.rdata),
160    CSRs.vlenb  -> (vlenb.w           -> vlenb.rdata),
161    CSRs.cycle  -> (cycle.w           -> cycle.rdata),
162    CSRs.time   -> (time.w            -> time.rdata),
163    CSRs.instret -> (instret.w        -> instret.rdata),
164  ) ++ hpmcounters.map(counter => (counter.addr -> (counter.w -> counter.rdata)))
165
166  val unprivilegedCSRMods: Seq[CSRModule[_]] = Seq(
167    fcsr,
168    vcsr,
169    vstart,
170    vl,
171    vtype,
172    vlenb,
173    cycle,
174    time,
175    instret,
176  ) ++ hpmcounters
177
178  val unprivilegedCSROutMap: SeqMap[Int, UInt] = SeqMap(
179    CSRs.fflags  -> fcsr.fflags.asUInt,
180    CSRs.frm     -> fcsr.frm.asUInt,
181    CSRs.fcsr    -> fcsr.rdata.asUInt,
182    CSRs.vstart  -> vstart.rdata.asUInt,
183    CSRs.vxsat   -> vcsr.vxsat.asUInt,
184    CSRs.vxrm    -> vcsr.vxrm.asUInt,
185    CSRs.vcsr    -> vcsr.rdata.asUInt,
186    CSRs.vl      -> vl.rdata.asUInt,
187    CSRs.vtype   -> vtype.rdata.asUInt,
188    CSRs.vlenb   -> vlenb.rdata.asUInt,
189    CSRs.cycle   -> cycle.rdata,
190    CSRs.time    -> time.rdata,
191    CSRs.instret -> instret.rdata,
192  ) ++ hpmcounters.map(counter => (counter.addr -> counter.rdata))
193}
194
195class CSRVTypeBundle extends CSRBundle {
196  val VILL  = RO(  63)
197  val VMA   = RO(   7)
198  val VTA   = RO(   6)
199  val VSEW  = RO(5, 3)
200  val VLMUL = RO(2, 0)
201}
202
203class CSRFrmBundle extends CSRBundle {
204  val FRM = WARL(2, 0, wNoFilter)
205}
206
207class CSRFFlagsBundle extends CSRBundle {
208  val NX = WARL(0, wNoFilter)
209  val UF = WARL(1, wNoFilter)
210  val OF = WARL(2, wNoFilter)
211  val DZ = WARL(3, wNoFilter)
212  val NV = WARL(4, wNoFilter)
213}
214
215object VlenbField extends CSREnum with ROApply {
216  val init = Value((VLEN / 8).U)
217}
218
219trait HasMHPMSink { self: CSRModule[_] =>
220  val mHPM = IO(Input(new Bundle {
221    val cycle   = UInt(64.W)
222    // ValidIO is used to update time reg
223    val time    = ValidIO(UInt(64.W))
224    val instret = UInt(64.W)
225    val hpmcounters = Vec(perfCntNum, UInt(XLEN.W))
226  }))
227  val v = IO(Input(Bool()))
228  val htimedelta = IO(Input(UInt(64.W)))
229}
230