1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.DelayN 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30import xiangshan.backend.fu.FuType 31import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 32import xiangshan.backend.fu.fpu.Bundles.Frm 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrio = OptionWrapper(params.hasCSR, new CSRFileIO) 39 val fenceio = OptionWrapper(params.hasFence, new FenceIO) 40 val frm = OptionWrapper(params.needSrcFrm, Input(Frm())) 41 val vxrm = OptionWrapper(params.needSrcVxrm, Input(Vxrm())) 42 val vtype = OptionWrapper(params.writeVType, new VType) 43} 44 45class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 46 override def shouldBeInlined: Boolean = false 47 48 lazy val module = new ExeUnitImp(this)(p, exuParams) 49} 50 51class ExeUnitImp( 52 override val wrapper: ExeUnit 53)(implicit 54 p: Parameters, exuParams: ExeUnitParams 55) extends LazyModuleImp(wrapper) with HasXSParameter{ 56 private val fuCfgs = exuParams.fuConfigs 57 58 val io = IO(new ExeUnitIO(exuParams)) 59 60 val funcUnits = fuCfgs.map(cfg => { 61 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 62 val module = cfg.fuGen(p, cfg) 63 module 64 }) 65 66 if (EnableClockGate) { 67 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 68 val clk_en = WireInit(false.B) 69 val fuVld_en = WireInit(false.B) 70 val fuVld_en_reg = RegInit(false.B) 71 val uncer_en_reg = RegInit(false.B) 72 73 val lat0 = FuType.isLat0(io.in.bits.fuType) 74 val latN = FuType.isLatN(io.in.bits.fuType) 75 val uncerLat = FuType.isUncerLat(io.in.bits.fuType) 76 77 def lat: Int = cfg.latency.latencyVal.getOrElse(0) 78 79 val fuVldVec = (io.in.valid && latN) +: Seq.fill(lat)(RegInit(false.B)) 80 val fuRdyVec = Seq.fill(lat)(Wire(Bool())) :+ io.out.ready 81 82 for (i <- 0 until lat) { 83 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 84 } 85 86 for (i <- 1 to lat) { 87 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 88 fuVldVec(i) := fuVldVec(i - 1) 89 }.elsewhen(fuRdyVec(i)) { 90 fuVldVec(i) := false.B 91 } 92 } 93 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 94 fuVld_en_reg := fuVld_en 95 96 when(uncerLat && io.in.fire) { 97 uncer_en_reg := true.B 98 }.elsewhen(uncerLat && io.out.fire) { 99 uncer_en_reg := false.B 100 } 101 102 when(lat0 && io.in.fire) { 103 clk_en := true.B 104 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 105 clk_en := true.B 106 }.elsewhen(uncerLat && io.in.fire || uncer_en_reg) { 107 clk_en := true.B 108 } 109 110 if (cfg.ckAlwaysEn) { 111 clk_en := true.B 112 } 113 114 val clk_gate = Module(new ClockGate) 115 clk_gate.io.TE := false.B 116 clk_gate.io.E := clk_en 117 clk_gate.io.CK := clock 118 fu.clock := clk_gate.io.Q 119 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 120 } 121 } 122 123 val busy = RegInit(false.B) 124 if (exuParams.latencyCertain){ 125 busy := false.B 126 } 127 else { 128 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 129 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 130 busy := false.B 131 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 132 busy := false.B 133 }.elsewhen(io.out.fire) { 134 busy := false.B 135 }.elsewhen(io.in.fire) { 136 busy := true.B 137 } 138 } 139 140 exuParams.wbPortConfigs.map{ 141 x => x match { 142 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 143 s"${exuParams.name}: WbPort must priority=0 or priority=1") 144 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 145 s"${exuParams.name}: WbPort must priority=0 or priority=1") 146 case _ => 147 } 148 } 149 val intWbPort = exuParams.getIntWBPort 150 if (intWbPort.isDefined){ 151 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 152 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 153 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 154 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 155 samePort.wbPortConfigs.map( 156 x => x match { 157 case IntWB(port, priority) => { 158 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 159 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 160 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 161 } 162 case _ => 163 } 164 ) 165 ) 166 } 167 val vfWbPort = exuParams.getVfWBPort 168 if (vfWbPort.isDefined) { 169 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 170 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 171 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 172 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 173 samePort.wbPortConfigs.map( 174 x => x match { 175 case VfWB(port, priority) => { 176 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 177 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 178 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 179 } 180 case _ => 181 } 182 ) 183 ) 184 } 185 if(backendParams.debugEn) { 186 dontTouch(io.out.ready) 187 } 188 // rob flush --> funcUnits 189 funcUnits.zipWithIndex.foreach { case (fu, i) => 190 fu.io.flush <> io.flush 191 } 192 193 def acceptCond(input: ExuInput): Seq[Bool] = { 194 input.params.fuConfigs.map(_.fuSel(input)) 195 } 196 197 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 198 199 // ExeUnit.in <---> Dispatcher.in 200 in1ToN.io.in.valid := io.in.valid && !busy 201 in1ToN.io.in.bits := io.in.bits 202 io.in.ready := !busy && in1ToN.io.in.ready 203 204 // Dispatcher.out <---> FunctionUnits 205 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 206 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 207 sink.valid := source.valid 208 source.ready := sink.ready 209 210 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 211 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 212 sink.bits.data.imm := source.bits.imm 213 sink.bits.ctrl.fuOpType := source.bits.fuOpType 214 sink.bits.ctrl.robIdx := source.bits.robIdx 215 sink.bits.ctrl.pdest := source.bits.pdest 216 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 217 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 218 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 219 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 220 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 221 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 222 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 223 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 224 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 225 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 226 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 227 } 228 229 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 230 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 231 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 232 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 233 234 // Assume that one fu can only write int or fp or vec, 235 // otherwise, wenVec should be assigned to wen in fu. 236 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 237 private val fuFpWenVec = funcUnits.map(x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 238 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 239 // FunctionUnits <---> ExeUnit.out 240 io.out.valid := Cat(fuOutValidOH).orR 241 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 242 243 // select one fu's result 244 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 245 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 246 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 247 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 248 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 249 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 250 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 251 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 252 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 253 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 254 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 255 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 256 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 257 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 258 259 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 260 fuio => 261 exuio <> fuio 262 fuio.exception := DelayN(exuio.exception, 2) 263 })) 264 265 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 266 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 267 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 268 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 269 270 // debug info 271 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 272 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 273 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 274} 275 276class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 277 val in = Flipped(DecoupledIO(gen)) 278 279 val out = Vec(n, DecoupledIO(gen)) 280} 281 282class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 283 (implicit p: Parameters) 284 extends Module { 285 286 val io = IO(new DispatcherIO(gen, n)) 287 288 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 289 290 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 291 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 292 293 io.out.zipWithIndex.foreach { case (out, i) => 294 out.valid := acceptVec(i) && io.in.valid 295 out.bits := io.in.bits 296 } 297 298 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 299} 300 301class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 302 val flush = Flipped(ValidIO(new Redirect())) 303 val in = Flipped(DecoupledIO(new MemExuInput())) 304 val out = DecoupledIO(new MemExuOutput()) 305} 306 307class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 308 val io = IO(new MemExeUnitIO) 309 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 310 fu.io.flush := io.flush 311 fu.io.in.valid := io.in.valid 312 io.in.ready := fu.io.in.ready 313 314 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 315 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 316 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 317 fu.io.in.bits.data.imm := io.in.bits.uop.imm 318 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 319 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 320 321 io.out.valid := fu.io.out.valid 322 fu.io.out.ready := io.out.ready 323 324 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 325 io.out.bits.data := fu.io.out.bits.res.data 326 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 327 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 328 io.out.bits.uop.fuType := io.in.bits.uop.fuType 329 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 330 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 331 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 332 333 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 334} 335