1package xiangshan.backend.fu.vector 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.fu.FuConfig.VialuCfg 7import xiangshan.backend.fu.vector.Bundles.VConfig 8import xiangshan.backend.fu.vector.utils.ScalaDupToVector 9import xiangshan.backend.fu.{FuConfig, FuncUnit, HasPipelineReg} 10import yunsuan.VialuFixType 11 12trait VecFuncUnitAlias { this: FuncUnit => 13 protected val inCtrl = io.in.bits.ctrl 14 protected val inData = io.in.bits.data 15 protected val vecCtrl = inCtrl.vpu.get 16 17 protected val vill = vecCtrl.vill 18 protected val vma = vecCtrl.vma 19 protected val vta = vecCtrl.vta 20 protected val vsew = vecCtrl.vsew 21 protected val vlmul = vecCtrl.vlmul 22 protected val vm = vecCtrl.vm 23 protected val vstart = vecCtrl.vstart 24 25 protected val frm = if(cfg.needSrcFrm) io.frm.get else 0.U 26 protected val vxrm = if(cfg.needSrcVxrm) io.vxrm.get else 0.U 27 protected val vuopIdx = vecCtrl.vuopIdx 28 protected val nf = 0.U // No need to handle nf in vector arith unit 29 30 protected val fuOpType = inCtrl.fuOpType 31 protected val isNarrow = vecCtrl.isNarrow 32 protected val isExt = vecCtrl.isExt 33 protected val isMove = vecCtrl.isMove 34 // swap vs1 and vs2, used by vrsub, etc 35 protected val isReverse = vecCtrl.isReverse 36 37 protected val allMaskTrue = VecInit(Seq.fill(VLEN)(true.B)).asUInt 38 protected val allMaskFalse = VecInit(Seq.fill(VLEN)(false.B)).asUInt 39 40 // vadc.vv, vsbc.vv need this 41 protected val needClearMask: Bool = if(cfg == VialuCfg) VialuFixType.needClearMask(inCtrl.fuOpType) else false.B 42 43 // There is no difference between control-dependency or data-dependency for function unit, 44 // but spliting these in ctrl or data bundles is easy to coding. 45 protected val srcMask: UInt = if(!cfg.maskWakeUp) inCtrl.vpu.get.vmask else { 46 MuxCase(inData.getSrcMask, Seq( 47 needClearMask -> allMaskFalse, 48 vm -> allMaskTrue 49 )) 50 } 51 protected val srcVConfig: VConfig = if(!cfg.vconfigWakeUp) inCtrl.vpu.get.vconfig else inData.getSrcVConfig.asTypeOf(new VConfig) 52 protected val vl = srcVConfig.vl 53} 54 55class VecPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 56 with HasPipelineReg 57 with VecFuncUnitAlias 58{ 59 private val src0 = inData.src(0) 60 private val src1 = WireInit(inData.src(1)) // vs2 only 61 if(cfg == FuConfig.VfaluCfg){ 62 val vs2Fold = Wire(UInt(VLEN.W)) 63 vs2Fold := Mux1H( 64 Seq( 65 vecCtrl.fpu.isFoldTo1_2 -> inData.src(1)(VLEN/1-1, VLEN/2), 66 vecCtrl.fpu.isFoldTo1_4 -> inData.src(1)(VLEN/2-1, VLEN/4), 67 vecCtrl.fpu.isFoldTo1_8 -> inData.src(1)(VLEN/4-1, VLEN/8), 68 ) 69 ) 70 src1 := Mux(vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8, vs2Fold, inData.src(1)) 71 } 72 protected val vs2 = Mux(isReverse, src0, src1) 73 protected val vs1 = Mux(isReverse, src1, src0) 74 protected val oldVd = inData.src(2) 75 76 protected val outCtrl = ctrlVec.last 77 protected val outData = dataVec.last 78 79 protected val outVecCtrl = outCtrl.vpu.get 80 protected val outVm = outVecCtrl.vm 81 82 // vadc.vv, vsbc.vv need this 83 protected val outNeedClearMask: Bool = if(cfg == VialuCfg) VialuFixType.needClearMask(outCtrl.fuOpType) else false.B 84 protected val outVConfig = if(!cfg.vconfigWakeUp) outCtrl.vpu.get.vconfig else outData.getSrcVConfig.asTypeOf(new VConfig) 85 protected val outVl = outVConfig.vl 86 protected val outVstart = outVecCtrl.vstart 87 protected val outOldVd = outData.src(2) 88 // There is no difference between control-dependency or data-dependency for function unit, 89 // but spliting these in ctrl or data bundles is easy to coding. 90 protected val outSrcMask: UInt = if (!cfg.maskWakeUp) outCtrl.vpu.get.vmask else { 91 MuxCase( 92 outData.getSrcMask, Seq( 93 outNeedClearMask -> allMaskFalse, 94 outVm -> allMaskTrue 95 ) 96 ) 97 } 98 99 override def latency: Int = cfg.latency.latencyVal.get 100 101} 102