| #
0fbf39af |
| 13-Jun-2024 |
lewislzh <[email protected]> |
VPU: fix vfreduction bug; remove redundant logic for scalar compute (#3065)
|
| #
d33803b9 |
| 19-Mar-2024 |
lewislzh <[email protected]> |
vfexu: remove isreverse from vecfuncunit
|
| #
20f53972 |
| 31-Mar-2024 |
sinceforYy <[email protected]> |
rv64v: fix vfalu timing
|
| #
17985fbb |
| 01-Feb-2024 |
Ziyue Zhang <[email protected]> |
rv64v: fix vxrm and frm connection for vector instructions
|
| #
395c8649 |
| 04-Jan-2024 |
Ziyue-Zhang <[email protected]> |
rv64v: add f2v to remove all fs1 duplicate logic (#2613)
* rv64v: add f2v to remove all fs1 duplicate logic
* rv64v: use IntFPToVec module for i2v and f2v
|
| #
daae8f22 |
| 25-Dec-2023 |
Ziyue Zhang <[email protected]> |
rv64v: fix vector move instruction
|
| #
83ba63b3 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge error
|
| #
9d3cebe7 |
| 28-Sep-2023 |
chengguanghui <[email protected]> |
vfcvt rtl: fixed cvt fu
|
| #
582849ff |
| 02-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: support unordered vfreduction
|
| #
d16a780c |
| 29-May-2023 |
Xuan Hu <[email protected]> |
vector: fix source data of vmadd and vnmsub
* The input of VIMac data module should be exchanged when opcode is vmadd or vnmsub, since source data are not exchanged in data module.
|
| #
2569173e |
| 26-May-2023 |
Xuan Hu <[email protected]> |
vector: update vialufix wrapper
|
| #
ffc8dae6 |
| 19-May-2023 |
Xuan Hu <[email protected]> |
vector: fix reverse signal
|
| #
42475509 |
| 18-May-2023 |
Xuan Hu <[email protected]> |
vector: add scala data duplicated to vector data path
|
| #
70478f41 |
| 17-May-2023 |
Xuan Hu <[email protected]> |
vector: fix mask src error
|
| #
35d005df |
| 22-May-2023 |
Xuan Hu <[email protected]> |
vector: add VIAluFix wrapper and related parameters
|