1package xiangshan.backend.fu.vector 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.fu.vector.Bundles.VConfig 7import xiangshan.backend.fu.{FuConfig, FuncUnit, HasPipelineReg} 8import yunsuan.VialuFixType 9 10trait VecFuncUnitAlias { this: FuncUnit => 11 protected val inCtrl = io.in.bits.ctrl 12 protected val inData = io.in.bits.data 13 protected val vecCtrl = inCtrl.vpu.get 14 15 protected val vill = vecCtrl.vill 16 protected val vma = vecCtrl.vma 17 protected val vta = vecCtrl.vta 18 protected val vsew = vecCtrl.vsew 19 protected val vlmul = vecCtrl.vlmul 20 protected val vm = vecCtrl.vm 21 protected val vstart = vecCtrl.vstart 22 23 protected val frm = vecCtrl.frm 24 protected val vxrm = vecCtrl.vxrm 25 protected val vuopIdx = vecCtrl.vuopIdx 26 protected val nf = vecCtrl.frm 27 28 protected val fuOpType = inCtrl.fuOpType 29 protected val isNarrow = vecCtrl.isNarrow 30 protected val isExt = vecCtrl.isExt 31 protected val isMove = vecCtrl.isMove 32 protected val isReverse = vecCtrl.isReverse 33 34 private val allMaskTrue = VecInit(Seq.fill(VLEN)(true.B)).asUInt 35 36 // There is no difference between control-dependency or data-dependency for function unit, 37 // but spliting these in ctrl or data bundles is easy to coding. 38 protected val srcMask = if(!cfg.maskWakeUp) inCtrl.vpu.get.vmask else Mux(vm, allMaskTrue, inData.getSrcMask) 39 protected val srcVConfig = if(!cfg.vconfigWakeUp) inCtrl.vpu.get.vconfig else inData.getSrcVConfig.asTypeOf(new VConfig) 40 41 // swap vs1 and vs2, used by vrsub, etc 42 val needReverse = VialuFixType.needReverse(inCtrl.fuOpType) 43 // vadc.vv, vsbc.vv need this 44 val needClearMask = VialuFixType.needClearMask(inCtrl.fuOpType) 45 46} 47 48class VecPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 49 with HasPipelineReg 50 with VecFuncUnitAlias 51{ 52 53 override def latency: Int = cfg.latency.latencyVal.get 54 55} 56