xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala (revision 01cdded87283f55be427ca849d18baa3e9459c2d) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import chisel3.experimental.BundleLiterals._
6import org.chipsalliance.cde.config.Parameters
7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL, _}
8import xiangshan.backend.fu.NewCSR.CSRFunc._
9import xiangshan.backend.fu.fpu.Bundles.Fflags
10import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxsat}
11
12object CSRBundles {
13  class XtvecBundle extends CSRBundle {
14    val mode = XtvecMode(1, 0, wNoFilter)
15    val addr = WARL(63, 2, wNoFilter)
16  }
17
18  class CauseBundle extends CSRBundle {
19    val Interrupt = RW(63)
20    val ExceptionCode = RW(62, 0)
21  }
22
23  class Counteren extends CSRBundle {
24    val CY = RW(0)
25    val TM = RW(1)
26    val IR = RW(2)
27    val HPM = RW(31, 3)
28  }
29
30  class OneFieldBundle extends CSRBundle {
31    val ALL = RW(63, 0)
32  }
33
34  class Envcfg extends CSRBundle {
35    val STCE  = RO(    63).withReset(0.U)
36    val PBMTE = RO(    62).withReset(0.U)
37    val ADUE  = RO(    61).withReset(0.U)
38    val PMM   = RO(33, 32).withReset(0.U)
39    val CBZE  = RO(     7).withReset(0.U)
40    val CBCFE = RO(     6).withReset(0.U)
41    val CBIE  = RO( 5,  4).withReset(0.U)
42    val FIOM  = RO(     0).withReset(0.U)
43  }
44
45  class PrivState extends Bundle {
46    val PRVM = PrivMode(0)
47    val V    = VirtMode(0)
48
49    def isModeHU: Bool = this.V === VirtMode.Off && this.PRVM === PrivMode.U
50
51    def isModeHS: Bool = this.V === VirtMode.Off && this.PRVM === PrivMode.S
52
53    def isModeHUorHS: Bool = this.V === VirtMode.Off && this.PRVM.isOneOf(PrivMode.S, PrivMode.U)
54
55    def isModeM: Bool = this.V === VirtMode.Off && this.PRVM === PrivMode.M
56
57    def isModeVU: Bool = this.V === VirtMode.On && this.PRVM === PrivMode.U
58
59    def isModeVS: Bool = this.V === VirtMode.On && this.PRVM === PrivMode.S
60
61    def isModeHUorVU: Bool = this.PRVM === PrivMode.U
62
63    def isVirtual: Bool = this.V === VirtMode.On
64
65    // VU < VS < HS < M
66    // HU < HS < M
67    def < (that: PrivState): Bool = {
68      (this.isVirtual && (that.isModeM || that.isModeHS)) ||
69        (this.V === that.V && this.PRVM < that.PRVM)
70    }
71
72    def > (that: PrivState): Bool = {
73      (that.isVirtual && (this.isModeM || this.isModeHS)) ||
74        (that.V === this.V && that.PRVM < this.PRVM)
75    }
76  }
77
78  object PrivState {
79    def ModeM: PrivState = WireInit((new PrivState).Lit(
80      _.PRVM -> PrivMode.M,
81      _.V    -> VirtMode.Off,
82    ))
83
84    def ModeHS: PrivState = WireInit((new PrivState).Lit(
85      _.PRVM -> PrivMode.S,
86      _.V    -> VirtMode.Off,
87    ))
88
89    def ModeHU: PrivState = WireInit((new PrivState).Lit(
90      _.PRVM -> PrivMode.U,
91      _.V    -> VirtMode.Off,
92    ))
93
94    def ModeVS: PrivState = WireInit((new PrivState).Lit(
95      _.PRVM -> PrivMode.S,
96      _.V    -> VirtMode.On,
97    ))
98
99    def ModeVU: PrivState = WireInit((new PrivState).Lit(
100      _.PRVM -> PrivMode.U,
101      _.V    -> VirtMode.On,
102    ))
103  }
104
105  class RobCommitCSR(implicit p: Parameters) extends Bundle {
106    // need contain 8x8
107    val instNum = ValidIO(UInt(7.W))
108    val fflags  = ValidIO(Fflags())
109    val fsDirty = Bool()
110    val vxsat   = ValidIO(Vxsat())
111    val vsDirty = Bool()
112    val vtype   = ValidIO(new CSRVTypeBundle)
113    val vl      = ValidIO(Vl())
114    val vstart  = ValidIO(Vstart())
115  }
116}
117