submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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feat(custom, csr): add two custom CSRs mcorepwr and mflushpwr to control power (#4164)

Co-authored-by: Zhu Yu <[email protected]>

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.

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feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s,

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s, h}.
* Support xenvcfg.CBIE = Flush(0b01)
* Decode
* Use the illegalInst and virtualInst conditions from CSR to assert
EX_II or EX_VI.
* Convert CBO.INVAL to CBO.FLUSH when envcfg.CBIE === EnvCBIE.Flush.

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RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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NewCSR: set legal init value to WARL Field

tmp-NewCSR: fix connection of CSR vector bundles

NewCSR: support Sstc extension

* Add `stimecmp` and `vstimecmp` CSR.
* Add `STIP` and `VSTIP` interrupt.
* Add `STCE` field in `menvcfg` and `henvcfg` to enable Sstc extension.

CSR: remove the enable bit for `svinval` extension

* Since `svinval` extension has been merged into the risc-v specification, there is no need to use custom config to disable it.

NewCSR: correct the produce of exception virtual address

* As specified by RISC-V specification, there are 3 different length of virtual address. They are `Bare`, `Sv39` and `Sv39x4`.
* The CSR mepc

NewCSR: correct the produce of exception virtual address

* As specified by RISC-V specification, there are 3 different length of virtual address. They are `Bare`, `Sv39` and `Sv39x4`.
* The CSR mepc and mtval use `Bare` address when the privilege mode is M mode or the satp.MODE is Bare.
* The CSR mepc and mtval use `Sv39` address when the privilege mode is S/U mode and the satp.MODE is Sv39 and when the privilege mode is VS/VU mode and the vsatp.MODE is Sv39.
* The CSR mepc and mtval use `Sv39x4` address when then privilege mode is VS/VU and the hgatp.MODE is Sv39x4 and the vsatp.MODE is Bare.
* The `Sv48` and `Sv48x4` support are provided partly in CSREvent for future usage.

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NewCSR: initialize mcounteren when reset

NewCSR: remove sdsid

NewCSR: refactor to make better verilog generation

NewCSR: fix bundle connection

NewCSR: fix unprivileged CSRs and permission check

* Add commit vstart
* Fix commit connection
* Fix permission check
* Fix mstatus.VS/FS initial with off
* Add fp/vec.off bundle to decode
* Flush w

NewCSR: fix unprivileged CSRs and permission check

* Add commit vstart
* Fix commit connection
* Fix permission check
* Fix mstatus.VS/FS initial with off
* Add fp/vec.off bundle to decode
* Flush when change vxrm
* Add more skip condition for mip and hip

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NewCSR: fix target pc of trap entry event

NewCSR: add TrapHandleModule to handle trap delegation and dispatch traps

NewCSR: add CSR events

NewCSR: modulized implementation

NewCSR: add Hypervisor CSRs

NewCSR: optimize dump fields using chisel3.reflect.DataMirror

NewCSR: add VirtualSupervisor CSRs

NewCSR: refactor VirtualSupervisor an

NewCSR: modulized implementation

NewCSR: add Hypervisor CSRs

NewCSR: optimize dump fields using chisel3.reflect.DataMirror

NewCSR: add VirtualSupervisor CSRs

NewCSR: refactor VirtualSupervisor and Hypervisor CSRs

* Make sure ValidIO etc function return CSREnumType not EnumType
* TODO: AIA for vs

NewCSR: add MachineLevel CSRs

NewCSR: fix alias relationship between hip, hvip and vsip

NewCSR: add SupervisorLevel CSRs

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