xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala (revision 8419d406575938fd0b239bcaed51ee8237b7a90b) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import chisel3.experimental.BundleLiterals._
6import org.chipsalliance.cde.config.Parameters
7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL, _}
8import xiangshan.backend.fu.NewCSR.CSRFunc._
9import xiangshan.backend.fu.fpu.Bundles.Fflags
10import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxsat}
11import xiangshan.frontend.BPUCtrl
12
13object CSRBundles {
14  class XtvecBundle extends CSRBundle {
15    val mode = XtvecMode(1, 0, wNoFilter)
16    val addr = WARL(63, 2, wNoFilter)
17  }
18
19  class CauseBundle extends CSRBundle {
20    val Interrupt = RW(63)
21    val ExceptionCode = RW(62, 0)
22  }
23
24  class Counteren extends CSRBundle {
25    val CY = RW(0)
26    val TM = RW(1)
27    val IR = RW(2)
28    val HPM = RW(31, 3)
29  }
30
31  class OneFieldBundle extends CSRBundle {
32    val ALL = RW(63, 0)
33  }
34
35  class Envcfg extends CSRBundle {
36    val STCE  = RO(    63).withReset(0.U)
37    val PBMTE = RO(    62).withReset(0.U)
38    val ADUE  = RO(    61).withReset(0.U)
39    val PMM   = RO(33, 32).withReset(0.U)
40    val CBZE  = RO(     7).withReset(0.U)
41    val CBCFE = RO(     6).withReset(0.U)
42    val CBIE  = RO( 5,  4).withReset(0.U)
43    val FIOM  = RO(     0).withReset(0.U)
44  }
45
46  class PrivState extends Bundle {
47    val PRVM = PrivMode(0)
48    val V    = VirtMode(0)
49
50    def isModeHU: Bool = this.V === VirtMode.Off && this.PRVM === PrivMode.U
51
52    def isModeHS: Bool = this.V === VirtMode.Off && this.PRVM === PrivMode.S
53
54    def isModeHUorHS: Bool = this.V === VirtMode.Off && this.PRVM.isOneOf(PrivMode.S, PrivMode.U)
55
56    def isModeM: Bool = this.V === VirtMode.Off && this.PRVM === PrivMode.M
57
58    def isModeVU: Bool = this.V === VirtMode.On && this.PRVM === PrivMode.U
59
60    def isModeVS: Bool = this.V === VirtMode.On && this.PRVM === PrivMode.S
61
62    def isModeHUorVU: Bool = this.PRVM === PrivMode.U
63
64    def isVirtual: Bool = this.V === VirtMode.On
65
66    // VU < VS < HS < M
67    // HU < HS < M
68    def < (that: PrivState): Bool = {
69      (this.isVirtual && (that.isModeM || that.isModeHS)) ||
70        (this.V === that.V && this.PRVM < that.PRVM)
71    }
72
73    def > (that: PrivState): Bool = {
74      (that.isVirtual && (this.isModeM || this.isModeHS)) ||
75        (that.V === this.V && that.PRVM < this.PRVM)
76    }
77  }
78
79  object PrivState {
80    def ModeM: PrivState = WireInit((new PrivState).Lit(
81      _.PRVM -> PrivMode.M,
82      _.V    -> VirtMode.Off,
83    ))
84
85    def ModeHS: PrivState = WireInit((new PrivState).Lit(
86      _.PRVM -> PrivMode.S,
87      _.V    -> VirtMode.Off,
88    ))
89
90    def ModeHU: PrivState = WireInit((new PrivState).Lit(
91      _.PRVM -> PrivMode.U,
92      _.V    -> VirtMode.Off,
93    ))
94
95    def ModeVS: PrivState = WireInit((new PrivState).Lit(
96      _.PRVM -> PrivMode.S,
97      _.V    -> VirtMode.On,
98    ))
99
100    def ModeVU: PrivState = WireInit((new PrivState).Lit(
101      _.PRVM -> PrivMode.U,
102      _.V    -> VirtMode.On,
103    ))
104  }
105
106  class RobCommitCSR(implicit p: Parameters) extends Bundle {
107    // need contain 8x8
108    val instNum = ValidIO(UInt(7.W))
109    val fflags  = ValidIO(Fflags())
110    val fsDirty = Bool()
111    val vxsat   = ValidIO(Vxsat())
112    val vsDirty = Bool()
113    val vtype   = ValidIO(new CSRVTypeBundle)
114    val vl      = ValidIO(Vl())
115    val vstart  = ValidIO(Vstart())
116  }
117
118  class CSRCustomState(implicit p: Parameters) extends Bundle {
119    // Prefetcher
120    val l1I_pf_enable = Output(Bool())
121    val l2_pf_enable = Output(Bool())
122    val l1D_pf_enable = Output(Bool())
123    val l1D_pf_train_on_hit = Output(Bool())
124    val l1D_pf_enable_agt = Output(Bool())
125    val l1D_pf_enable_pht = Output(Bool())
126    val l1D_pf_active_threshold = Output(UInt(4.W))
127    val l1D_pf_active_stride = Output(UInt(6.W))
128    val l1D_pf_enable_stride = Output(Bool())
129    val l2_pf_store_only = Output(Bool())
130    // ICache
131    val icache_parity_enable = Output(Bool())
132    // Labeled XiangShan
133    val dsid = Output(UInt(8.W)) // TODO: DsidWidth as parameter
134    // Load violation predictor
135    val lvpred_disable = Output(Bool())
136    val no_spec_load = Output(Bool())
137    val storeset_wait_store = Output(Bool())
138    val storeset_no_fast_wakeup = Output(Bool())
139    val lvpred_timeout = Output(UInt(5.W))
140    // Branch predictor
141    val bp_ctrl = Output(new BPUCtrl)
142    // Memory Block
143    val sbuffer_threshold = Output(UInt(4.W))
144    val ldld_vio_check_enable = Output(Bool())
145    val soft_prefetch_enable = Output(Bool())
146    val cache_error_enable = Output(Bool())
147    val uncache_write_outstanding_enable = Output(Bool())
148    // Rename
149    val fusion_enable = Output(Bool())
150    val wfi_enable = Output(Bool())
151    // Decode
152    val svinval_enable = Output(Bool())
153  }
154}
155