1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 // Seq(( 2048, 2, 8), 103 // ( 2048, 9, 8), 104 // ( 2048, 13, 8), 105 // ( 2048, 20, 8), 106 // ( 2048, 26, 8), 107 // ( 2048, 44, 8), 108 // ( 2048, 73, 8), 109 // ( 2048, 256, 8)), 110 Seq(( 4096, 8, 8), 111 ( 4096, 13, 8), 112 ( 4096, 32, 8), 113 ( 4096, 119, 8)), 114 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 115 // Sets Hist Tag 116 Seq(( 256, 4, 9), 117 ( 256, 8, 9), 118 ( 512, 13, 9), 119 ( 512, 16, 9), 120 ( 512, 32, 9)), 121 SCNRows: Int = 512, 122 SCNTables: Int = 4, 123 SCCtrBits: Int = 6, 124 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 125 numBr: Int = 2, 126 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 127 ((resp_in: BranchPredictionResp, p: Parameters) => { 128 val ftb = Module(new FTB()(p)) 129 val ubtb =Module(new FauFTB()(p)) 130 // val bim = Module(new BIM()(p)) 131 val tage = Module(new Tage_SC()(p)) 132 val ras = Module(new RAS()(p)) 133 val ittage = Module(new ITTage()(p)) 134 val preds = Seq(ubtb, tage, ftb, ittage, ras) 135 preds.map(_.io := DontCare) 136 137 // ubtb.io.resp_in(0) := resp_in 138 // bim.io.resp_in(0) := ubtb.io.resp 139 // btb.io.resp_in(0) := bim.io.resp 140 // tage.io.resp_in(0) := btb.io.resp 141 // loop.io.resp_in(0) := tage.io.resp 142 ubtb.io.in.bits.resp_in(0) := resp_in 143 tage.io.in.bits.resp_in(0) := ubtb.io.out 144 ftb.io.in.bits.resp_in(0) := tage.io.out 145 ittage.io.in.bits.resp_in(0) := ftb.io.out 146 ras.io.in.bits.resp_in(0) := ittage.io.out 147 148 (preds, ras.io.out) 149 }), 150 ICacheECCForceError: Boolean = false, 151 IBufSize: Int = 48, 152 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 153 DecodeWidth: Int = 6, 154 RenameWidth: Int = 6, 155 CommitWidth: Int = 8, 156 RobCommitWidth: Int = 8, 157 RabCommitWidth: Int = 6, 158 MaxUopSize: Int = 65, 159 EnableRenameSnapshot: Boolean = true, 160 RenameSnapshotNum: Int = 4, 161 FtqSize: Int = 64, 162 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 163 IntLogicRegs: Int = 32, 164 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 165 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 166 VCONFIG_IDX: Int = 32, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 20, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 64, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 dpParams: DispatchParameters = DispatchParameters( 185 IntDqSize = 16, 186 FpDqSize = 16, 187 LsDqSize = 18, 188 IntDqDeqWidth = 8, 189 FpDqDeqWidth = 6, 190 LsDqDeqWidth = 6, 191 ), 192 intPreg: PregParams = IntPregParams( 193 numEntries = 224, 194 numRead = None, 195 numWrite = None, 196 ), 197 vfPreg: VfPregParams = VfPregParams( 198 numEntries = 192, 199 numRead = None, 200 numWrite = None, 201 ), 202 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 203 LoadPipelineWidth: Int = 3, 204 StorePipelineWidth: Int = 2, 205 VecLoadPipelineWidth: Int = 1, 206 VecStorePipelineWidth: Int = 1, 207 VecMemSrcInWidth: Int = 2, 208 VecMemInstWbWidth: Int = 1, 209 VecMemDispatchWidth: Int = 1, 210 VecMemDispatchMaxNumber: Int = 16, 211 StoreBufferSize: Int = 16, 212 StoreBufferThreshold: Int = 7, 213 EnsbufferWidth: Int = 2, 214 LoadDependencyWidth: Int = 2, 215 // ============ VLSU ============ 216 VlMergeBufferSize: Int = 16, 217 VsMergeBufferSize: Int = 16, 218 UopWritebackWidth: Int = 1, 219 VLUopWritebackWidth: Int = 1, 220 VSUopWritebackWidth: Int = 1, 221 SplitBufferSize: Int = 8, 222 VSegmentBufferSize: Int = 8, 223 // ============================== 224 UncacheBufferSize: Int = 4, 225 EnableLoadToLoadForward: Boolean = false, 226 EnableFastForward: Boolean = true, 227 EnableLdVioCheckAfterReset: Boolean = true, 228 EnableSoftPrefetchAfterReset: Boolean = true, 229 EnableCacheErrorAfterReset: Boolean = true, 230 EnableAccurateLoadError: Boolean = true, 231 EnableUncacheWriteOutstanding: Boolean = false, 232 EnableStorePrefetchAtIssue: Boolean = false, 233 EnableStorePrefetchAtCommit: Boolean = false, 234 EnableAtCommitMissTrigger: Boolean = true, 235 EnableStorePrefetchSMS: Boolean = false, 236 EnableStorePrefetchSPB: Boolean = false, 237 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 238 MMUVmidLen: Int = 14, 239 ReSelectLen: Int = 7, // load replay queue replay select counter len 240 iwpuParameters: WPUParameters = WPUParameters( 241 enWPU = false, 242 algoName = "mmru", 243 isICache = true, 244 ), 245 dwpuParameters: WPUParameters = WPUParameters( 246 enWPU = false, 247 algoName = "mmru", 248 enCfPred = false, 249 isICache = false, 250 ), 251 itlbParameters: TLBParameters = TLBParameters( 252 name = "itlb", 253 fetchi = true, 254 useDmode = false, 255 NWays = 48, 256 ), 257 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 258 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 259 ldtlbParameters: TLBParameters = TLBParameters( 260 name = "ldtlb", 261 NWays = 48, 262 outReplace = false, 263 partialStaticPMP = true, 264 outsideRecvFlush = true, 265 saveLevel = true, 266 lgMaxSize = 4 267 ), 268 sttlbParameters: TLBParameters = TLBParameters( 269 name = "sttlb", 270 NWays = 48, 271 outReplace = false, 272 partialStaticPMP = true, 273 outsideRecvFlush = true, 274 saveLevel = true, 275 lgMaxSize = 4 276 ), 277 hytlbParameters: TLBParameters = TLBParameters( 278 name = "hytlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = true, 284 lgMaxSize = 4 285 ), 286 pftlbParameters: TLBParameters = TLBParameters( 287 name = "pftlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = true, 293 lgMaxSize = 4 294 ), 295 l2ToL1tlbParameters: TLBParameters = TLBParameters( 296 name = "l2tlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = true 302 ), 303 refillBothTlb: Boolean = false, 304 btlbParameters: TLBParameters = TLBParameters( 305 name = "btlb", 306 NWays = 48, 307 ), 308 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 309 NumPerfCounters: Int = 16, 310 icacheParameters: ICacheParameters = ICacheParameters( 311 tagECC = Some("parity"), 312 dataECC = Some("parity"), 313 replacer = Some("setplru"), 314 nMissEntries = 2, 315 nProbeEntries = 2, 316 nPrefetchEntries = 12, 317 nPrefBufferEntries = 32, 318 ), 319 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 320 tagECC = Some("secded"), 321 dataECC = Some("secded"), 322 replacer = Some("setplru"), 323 nMissEntries = 16, 324 nProbeEntries = 8, 325 nReleaseEntries = 18, 326 nMaxPrefetchEntry = 6, 327 )), 328 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 329 name = "l2", 330 ways = 8, 331 sets = 1024, // default 512KB L2 332 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 333 )), 334 L2NBanks: Int = 1, 335 usePTWRepeater: Boolean = false, 336 softTLB: Boolean = false, // dpi-c l1tlb debug only 337 softPTW: Boolean = false, // dpi-c l2tlb debug only 338 softPTWDelay: Int = 1 339){ 340 def vlWidth = log2Up(VLEN) + 1 341 342 /** 343 * the minimum element length of vector elements 344 */ 345 val minVecElen: Int = 8 346 347 /** 348 * the maximum number of elements in vector register 349 */ 350 val maxElemPerVreg: Int = VLEN / minVecElen 351 352 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 353 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 354 355 val intSchdParams = { 356 implicit val schdType: SchedulerType = IntScheduler() 357 SchdBlockParams(Seq( 358 IssueBlockParams(Seq( 359 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 360 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 361 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 362 IssueBlockParams(Seq( 363 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 364 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 365 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 366 IssueBlockParams(Seq( 367 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 368 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 369 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 370 IssueBlockParams(Seq( 371 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 372 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 373 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 374 ), 375 numPregs = intPreg.numEntries, 376 numDeqOutside = 0, 377 schdType = schdType, 378 rfDataWidth = intPreg.dataCfg.dataWidth, 379 numUopIn = dpParams.IntDqDeqWidth, 380 ) 381 } 382 val vfSchdParams = { 383 implicit val schdType: SchedulerType = VfScheduler() 384 SchdBlockParams(Seq( 385 IssueBlockParams(Seq( 386 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 387 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 388 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 389 IssueBlockParams(Seq( 390 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg, F2vCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 391 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 7, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 395 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 6, 1)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 396 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 397 ), 398 numPregs = vfPreg.numEntries, 399 numDeqOutside = 0, 400 schdType = schdType, 401 rfDataWidth = vfPreg.dataCfg.dataWidth, 402 numUopIn = dpParams.FpDqDeqWidth, 403 ) 404 } 405 406 val memSchdParams = { 407 implicit val schdType: SchedulerType = MemScheduler() 408 val rfDataWidth = 64 409 410 SchdBlockParams(Seq( 411 IssueBlockParams(Seq( 412 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 413 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 414 IssueBlockParams(Seq( 415 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 416 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 417 IssueBlockParams(Seq( 418 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 419 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 420 IssueBlockParams(Seq( 421 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 422 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 423 IssueBlockParams(Seq( 424 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 425 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 426 IssueBlockParams(Seq( 427 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 428 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 429 IssueBlockParams(Seq( 430 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), VfRD(12, Int.MaxValue)))), 431 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 432 IssueBlockParams(Seq( 433 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), VfRD(13, Int.MaxValue)))), 434 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 435 ), 436 numPregs = intPreg.numEntries max vfPreg.numEntries, 437 numDeqOutside = 0, 438 schdType = schdType, 439 rfDataWidth = rfDataWidth, 440 numUopIn = dpParams.LsDqDeqWidth, 441 ) 442 } 443 444 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 445 446 def iqWakeUpParams = { 447 Seq( 448 WakeUpConfig( 449 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 450 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 451 ), 452 WakeUpConfig( 453 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "LDU0", "LDU1", "LDU2") -> 454 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 455 ), 456 WakeUpConfig( 457 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 458 Seq("STD0", "STD1") 459 ), 460 ).flatten 461 } 462 463 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 464 465 val backendParams: BackendParams = backend.BackendParams( 466 Map( 467 IntScheduler() -> intSchdParams, 468 VfScheduler() -> vfSchdParams, 469 MemScheduler() -> memSchdParams, 470 ), 471 Seq( 472 intPreg, 473 vfPreg, 474 fakeIntPreg 475 ), 476 iqWakeUpParams, 477 ) 478} 479 480case object DebugOptionsKey extends Field[DebugOptions] 481 482case class DebugOptions 483( 484 FPGAPlatform: Boolean = false, 485 EnableDifftest: Boolean = false, 486 AlwaysBasicDiff: Boolean = true, 487 EnableDebug: Boolean = false, 488 EnablePerfDebug: Boolean = true, 489 UseDRAMSim: Boolean = false, 490 EnableConstantin: Boolean = false, 491 EnableChiselDB: Boolean = false, 492 AlwaysBasicDB: Boolean = true, 493 EnableTopDown: Boolean = false, 494 EnableRollingDB: Boolean = false 495) 496 497trait HasXSParameter { 498 499 implicit val p: Parameters 500 501 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 502 503 val coreParams = p(XSCoreParamsKey) 504 val env = p(DebugOptionsKey) 505 506 val XLEN = coreParams.XLEN 507 val VLEN = coreParams.VLEN 508 val ELEN = coreParams.ELEN 509 val HSXLEN = coreParams.HSXLEN 510 val minFLen = 32 511 val fLen = 64 512 val hartIdLen = p(MaxHartIdBits) 513 def xLen = XLEN 514 515 val HasMExtension = coreParams.HasMExtension 516 val HasCExtension = coreParams.HasCExtension 517 val HasHExtension = coreParams.HasHExtension 518 val HasDiv = coreParams.HasDiv 519 val HasIcache = coreParams.HasICache 520 val HasDcache = coreParams.HasDCache 521 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 522 val GPAddrBits = coreParams.GPAddrBits 523 val VAddrBits = { 524 if(HasHExtension){ 525 coreParams.GPAddrBits 526 }else{ 527 coreParams.VAddrBits 528 } 529 } // VAddrBits is Virtual Memory addr bits 530 531 val AsidLength = coreParams.AsidLength 532 val VmidLength = coreParams.VmidLength 533 val ReSelectLen = coreParams.ReSelectLen 534 val AddrBytes = AddrBits / 8 // unused 535 val DataBits = XLEN 536 val DataBytes = DataBits / 8 537 val VDataBytes = VLEN / 8 538 val HasFPU = coreParams.HasFPU 539 val HasVPU = coreParams.HasVPU 540 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 541 val FetchWidth = coreParams.FetchWidth 542 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 543 val EnableBPU = coreParams.EnableBPU 544 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 545 val EnableRAS = coreParams.EnableRAS 546 val EnableLB = coreParams.EnableLB 547 val EnableLoop = coreParams.EnableLoop 548 val EnableSC = coreParams.EnableSC 549 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 550 val HistoryLength = coreParams.HistoryLength 551 val EnableGHistDiff = coreParams.EnableGHistDiff 552 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 553 val EnableClockGate = coreParams.EnableClockGate 554 val UbtbGHRLength = coreParams.UbtbGHRLength 555 val UbtbSize = coreParams.UbtbSize 556 val EnableFauFTB = coreParams.EnableFauFTB 557 val FtbSize = coreParams.FtbSize 558 val FtbWays = coreParams.FtbWays 559 val RasSize = coreParams.RasSize 560 val RasSpecSize = coreParams.RasSpecSize 561 val RasCtrSize = coreParams.RasCtrSize 562 563 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 564 coreParams.branchPredictor(resp_in, p) 565 } 566 val numBr = coreParams.numBr 567 val TageTableInfos = coreParams.TageTableInfos 568 val TageBanks = coreParams.numBr 569 val SCNRows = coreParams.SCNRows 570 val SCCtrBits = coreParams.SCCtrBits 571 val SCHistLens = coreParams.SCHistLens 572 val SCNTables = coreParams.SCNTables 573 574 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 575 case ((n, cb), h) => (n, cb, h) 576 } 577 val ITTageTableInfos = coreParams.ITTageTableInfos 578 type FoldedHistoryInfo = Tuple2[Int, Int] 579 val foldedGHistInfos = 580 (TageTableInfos.map{ case (nRows, h, t) => 581 if (h > 0) 582 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 583 else 584 Set[FoldedHistoryInfo]() 585 }.reduce(_++_).toSet ++ 586 SCTableInfos.map{ case (nRows, _, h) => 587 if (h > 0) 588 Set((h, min(log2Ceil(nRows/TageBanks), h))) 589 else 590 Set[FoldedHistoryInfo]() 591 }.reduce(_++_).toSet ++ 592 ITTageTableInfos.map{ case (nRows, h, t) => 593 if (h > 0) 594 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 595 else 596 Set[FoldedHistoryInfo]() 597 }.reduce(_++_) ++ 598 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 599 ).toList 600 601 602 603 val CacheLineSize = coreParams.CacheLineSize 604 val CacheLineHalfWord = CacheLineSize / 16 605 val ExtHistoryLength = HistoryLength + 64 606 val ICacheECCForceError = coreParams.ICacheECCForceError 607 val IBufSize = coreParams.IBufSize 608 val IBufNBank = coreParams.IBufNBank 609 val backendParams: BackendParams = coreParams.backendParams 610 val DecodeWidth = coreParams.DecodeWidth 611 val RenameWidth = coreParams.RenameWidth 612 val CommitWidth = coreParams.CommitWidth 613 val RobCommitWidth = coreParams.RobCommitWidth 614 val RabCommitWidth = coreParams.RabCommitWidth 615 val MaxUopSize = coreParams.MaxUopSize 616 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 617 val RenameSnapshotNum = coreParams.RenameSnapshotNum 618 val FtqSize = coreParams.FtqSize 619 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 620 val IntLogicRegs = coreParams.IntLogicRegs 621 val FpLogicRegs = coreParams.FpLogicRegs 622 val VecLogicRegs = coreParams.VecLogicRegs 623 val VCONFIG_IDX = coreParams.VCONFIG_IDX 624 val IntPhyRegs = coreParams.intPreg.numEntries 625 val VfPhyRegs = coreParams.vfPreg.numEntries 626 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 627 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 628 val RobSize = coreParams.RobSize 629 val RabSize = coreParams.RabSize 630 val VTypeBufferSize = coreParams.VTypeBufferSize 631 /** 632 * the minimum element length of vector elements 633 */ 634 val minVecElen: Int = coreParams.minVecElen 635 636 /** 637 * the maximum number of elements in vector register 638 */ 639 val maxElemPerVreg: Int = coreParams.maxElemPerVreg 640 641 val IntRefCounterWidth = log2Ceil(RobSize) 642 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 643 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 644 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 645 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 646 val LoadQueueRARSize = coreParams.LoadQueueRARSize 647 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 648 val RollbackGroupSize = coreParams.RollbackGroupSize 649 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 650 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 651 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 652 val StoreQueueSize = coreParams.StoreQueueSize 653 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 654 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 655 val VlsQueueSize = coreParams.VlsQueueSize 656 val dpParams = coreParams.dpParams 657 658 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 659 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 660 661 val NumRedirect = backendParams.numRedirect 662 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 663 val FtqRedirectAheadNum = NumRedirect 664 val LoadPipelineWidth = coreParams.LoadPipelineWidth 665 val StorePipelineWidth = coreParams.StorePipelineWidth 666 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 667 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 668 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 669 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 670 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 671 val VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 672 val StoreBufferSize = coreParams.StoreBufferSize 673 val StoreBufferThreshold = coreParams.StoreBufferThreshold 674 val EnsbufferWidth = coreParams.EnsbufferWidth 675 val LoadDependencyWidth = coreParams.LoadDependencyWidth 676 val VlMergeBufferSize = coreParams.VlMergeBufferSize 677 val VsMergeBufferSize = coreParams.VsMergeBufferSize 678 val UopWritebackWidth = coreParams.UopWritebackWidth 679 val VLUopWritebackWidth = coreParams.VLUopWritebackWidth 680 val VSUopWritebackWidth = coreParams.VSUopWritebackWidth 681 val SplitBufferSize = coreParams.SplitBufferSize 682 val VSegmentBufferSize = coreParams.VSegmentBufferSize 683 val UncacheBufferSize = coreParams.UncacheBufferSize 684 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 685 val EnableFastForward = coreParams.EnableFastForward 686 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 687 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 688 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 689 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 690 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 691 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 692 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 693 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 694 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 695 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 696 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 697 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 698 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 699 val asidLen = coreParams.MMUAsidLen 700 val vmidLen = coreParams.MMUVmidLen 701 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 702 val refillBothTlb = coreParams.refillBothTlb 703 val iwpuParam = coreParams.iwpuParameters 704 val dwpuParam = coreParams.dwpuParameters 705 val itlbParams = coreParams.itlbParameters 706 val ldtlbParams = coreParams.ldtlbParameters 707 val sttlbParams = coreParams.sttlbParameters 708 val hytlbParams = coreParams.hytlbParameters 709 val pftlbParams = coreParams.pftlbParameters 710 val l2ToL1Params = coreParams.l2ToL1tlbParameters 711 val btlbParams = coreParams.btlbParameters 712 val l2tlbParams = coreParams.l2tlbParameters 713 val NumPerfCounters = coreParams.NumPerfCounters 714 715 val instBytes = if (HasCExtension) 2 else 4 716 val instOffsetBits = log2Ceil(instBytes) 717 718 val icacheParameters = coreParams.icacheParameters 719 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 720 721 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 722 // for constrained LR/SC loop 723 val LRSCCycles = 64 724 // for lr storm 725 val LRSCBackOff = 8 726 727 // cache hierarchy configurations 728 val l1BusDataWidth = 256 729 730 // load violation predict 731 val ResetTimeMax2Pow = 20 //1078576 732 val ResetTimeMin2Pow = 10 //1024 733 // wait table parameters 734 val WaitTableSize = 1024 735 val MemPredPCWidth = log2Up(WaitTableSize) 736 val LWTUse2BitCounter = true 737 // store set parameters 738 val SSITSize = WaitTableSize 739 val LFSTSize = 32 740 val SSIDWidth = log2Up(LFSTSize) 741 val LFSTWidth = 4 742 val StoreSetEnable = true // LWT will be disabled if SS is enabled 743 val LFSTEnable = true 744 745 val PCntIncrStep: Int = 6 746 val numPCntHc: Int = 25 747 val numPCntPtw: Int = 19 748 749 val numCSRPCntFrontend = 8 750 val numCSRPCntCtrl = 8 751 val numCSRPCntLsu = 8 752 val numCSRPCntHc = 5 753 val printEventCoding = true 754 755 // Parameters for Sdtrig extension 756 protected val TriggerNum = 4 757 protected val TriggerChainMaxLength = 2 758} 759