1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //mem status 30 val mem = OptionWrapper(params.isMemAddrIQ, new StatusMemPart) 31 //vector mem status 32 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 55 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 56 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 57 } 58 59 class StatusMemPart(implicit p:Parameters) extends Bundle { 60 val waitForSqIdx = new SqPtr // generated by store data valid check 61 val waitForRobIdx = new RobPtr // generated by store set 62 val waitForStd = Bool() 63 val strictWait = Bool() 64 val sqIdx = new SqPtr 65 } 66 67 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 68 val sqIdx = new SqPtr 69 val lqIdx = new LqPtr 70 } 71 72 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 73 val robIdx = new RobPtr 74 val resp = RespType() 75 val fuType = FuType() 76 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 77 } 78 79 object RespType { 80 def apply() = UInt(2.W) 81 82 def isBlocked(resp: UInt) = { 83 resp === block 84 } 85 86 def succeed(resp: UInt) = { 87 resp === success 88 } 89 90 val block = "b00".U 91 val uncertain = "b01".U 92 val success = "b11".U 93 } 94 95 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 96 val status = new Status() 97 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 98 val payload = new DynInst() 99 } 100 101 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 102 val flush = Flipped(ValidIO(new Redirect)) 103 val enq = Flipped(ValidIO(new EntryBundle)) 104 //wakeup 105 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 106 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 107 //cancel 108 val og0Cancel = Input(ExuOH(backendParams.numExu)) 109 val og1Cancel = Input(ExuOH(backendParams.numExu)) 110 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 111 //deq sel 112 val deqSel = Input(Bool()) 113 val deqPortIdxWrite = Input(UInt(1.W)) 114 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 115 //trans sel 116 val transSel = Input(Bool()) 117 // mem only 118 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 119 val stIssuePtr = Input(new SqPtr) 120 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 121 }) 122 // vector mem only 123 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 124 val sqDeqPtr = Input(new SqPtr) 125 val lqDeqPtr = Input(new LqPtr) 126 }) 127 } 128 129 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 130 //status 131 val valid = Output(Bool()) 132 val canIssue = Output(Bool()) 133 val fuType = Output(FuType()) 134 val robIdx = Output(new RobPtr) 135 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 136 //src 137 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 138 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 139 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 140 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 141 //deq 142 val isFirstIssue = Output(Bool()) 143 val entry = ValidIO(new EntryBundle) 144 val deqPortIdxRead = Output(UInt(1.W)) 145 val issueTimerRead = Output(UInt(2.W)) 146 //trans 147 val enqReady = Output(Bool()) 148 val transEntry = ValidIO(new EntryBundle) 149 // debug 150 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 151 val entryInValid = Output(Bool()) 152 val entryOutDeqValid = Output(Bool()) 153 val entryOutTransValid = Output(Bool()) 154 } 155 156 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 157 val validRegNext = Bool() 158 val flushed = Bool() 159 val clear = Bool() 160 val canIssue = Bool() 161 val enqReady = Bool() 162 val deqSuccess = Bool() 163 val srcWakeup = Vec(params.numRegSrc, Bool()) 164 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 165 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 166 val srcCancelVec = Vec(params.numRegSrc, Bool()) 167 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 168 } 169 170 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 171 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 172 common.flushed := status.robIdx.needFlush(commonIn.flush) 173 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 174 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 175 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 176 common.canIssue := validReg && status.canIssue 177 common.enqReady := !validReg || common.clear 178 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 179 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 180 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 181 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 182 srcCancel := srcLoadCancel || ldTransCancel 183 } 184 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 185 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 186 if(params.hasIQWakeUp) { 187 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 188 } else { 189 loadDependencyOut := loadDependency 190 } 191 192 } 193 if(isEnq) { 194 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 195 } else { 196 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 197 } 198 } 199 200 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 201 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 202 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 203 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 204 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 205 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 206 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 207 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 208 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 209 val cancelVec = Vec(params.numRegSrc, Bool()) 210 val canIssueBypass = Bool() 211 } 212 213 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 214 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 215 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 216 ).toSeq.transpose 217 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 218 219 hasIQWakeupGet.cancelVec := common.srcCancelVec 220 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 221 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 222 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 223 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 224 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 225 case (exuOH, regExuOH) => 226 exuOH := 0.U.asTypeOf(exuOH) 227 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 228 } 229 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 230 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 231 if(isEnq) { 232 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 233 } else { 234 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 235 } 236 } 237 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 238 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 239 wakeupVec.asUInt.orR | state 240 }).asUInt.andR 241 } 242 243 244 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 245 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 246 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 247 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 248 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 249 case ((dep, originalDep), deqPortIdx) => 250 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 251 dep := (originalDep << 2).asUInt | 2.U 252 else 253 dep := originalDep << 1 254 } 255 } 256 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 257 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 258 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 259 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 260 case ((dep, originalDep), deqPortIdx) => 261 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 262 dep := (originalDep << 1).asUInt | 1.U 263 else 264 dep := originalDep 265 } 266 } 267 } 268 269 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 270 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 271 val cancelByLd = common.srcCancelVec.asUInt.orR 272 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 273 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 274 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 275 entryUpdate.status.robIdx := status.robIdx 276 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 277 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 278 val cancel = common.srcCancelVec(srcIdx) 279 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 280 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 281 val wakeup = common.srcWakeup(srcIdx) 282 srcStatusNext.psrc := srcStatus.psrc 283 srcStatusNext.srcType := srcStatus.srcType 284 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 285 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, Mux(srcStatus.dataSources.readBypass, DataSource.reg, srcStatus.dataSources.value)) 286 if(params.hasIQWakeUp) { 287 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 288 // T0: waked up by IQ, T1: reset timer as 1 289 wakeupByIQ -> 2.U, 290 // do not overflow 291 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 292 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 293 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 294 )) 295 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 296 srcStatusNext.srcLoadDependency := 297 Mux(wakeup, 298 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 299 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 300 } else { 301 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 302 } 303 } 304 entryUpdate.status.blocked := false.B 305 entryUpdate.status.issued := MuxCase(status.issued, Seq( 306 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 307 commonIn.deqSel -> true.B, 308 !status.srcReady -> false.B, 309 )) 310 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 311 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 312 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 313 entryUpdate.imm.foreach(_ := entryReg.imm.get) 314 entryUpdate.payload := entryReg.payload 315 if (params.isVecMemIQ) { 316 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 317 } 318 } 319 320 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 321 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 322 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 323 commonOut.valid := validReg 324 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 325 else common.canIssue && !common.flushed) 326 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 327 commonOut.robIdx := status.robIdx 328 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 329 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 330 } 331 commonOut.isFirstIssue := !status.firstIssue 332 commonOut.entry.valid := validReg 333 commonOut.entry.bits := entryReg 334 if(isEnq) { 335 commonOut.entry.bits.status := status 336 } 337 commonOut.issueTimerRead := status.issueTimer 338 commonOut.deqPortIdxRead := status.deqPortIdx 339 if(params.hasIQWakeUp) { 340 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 341 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 342 else VecInit(srcWakeupExuOH)) 343 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 344 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 345 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 346 } 347 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 348 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 349 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 350 status.srcStatus(srcIdx).srcLoadDependency) 351 else status.srcStatus(srcIdx).srcLoadDependency) 352 } 353 } else { 354 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 355 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 356 } 357 } 358 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 359 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 360 common.srcLoadDependencyOut(srcIdx), 361 status.srcStatus(srcIdx).srcLoadDependency) 362 else status.srcStatus(srcIdx).srcLoadDependency) 363 } 364 commonOut.enqReady := common.enqReady 365 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 366 commonOut.transEntry.bits := entryUpdate 367 // debug 368 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 369 commonOut.entryInValid := commonIn.enq.valid 370 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 371 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 372 if (params.isVecMemIQ) { 373 commonOut.uopIdx.get := entryReg.payload.uopIdx 374 } 375 } 376 377 def EntryMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 378 val enqValid = if(isEnq) commonIn.enq.valid && common.enqReady 379 else commonIn.enq.valid 380 val fromMem = commonIn.fromMem.get 381 val memStatus = entryReg.status.mem.get 382 val memStatusNext = entryRegNext.status.mem.get 383 val memStatusUpdate = entryUpdate.status.mem.get 384 385 when(enqValid) { 386 memStatusNext.waitForSqIdx := commonIn.enq.bits.status.mem.get.waitForSqIdx 387 // update by lfst at dispatch stage 388 memStatusNext.waitForRobIdx := commonIn.enq.bits.status.mem.get.waitForRobIdx 389 // new load inst don't known if it is blocked by store data ahead of it 390 memStatusNext.waitForStd := false.B 391 // update by ssit at rename stage 392 memStatusNext.strictWait := commonIn.enq.bits.status.mem.get.strictWait 393 memStatusNext.sqIdx := commonIn.enq.bits.status.mem.get.sqIdx 394 }.otherwise { 395 memStatusNext := memStatusUpdate 396 } 397 398 // load cannot be issued before older store, unless meet some condition 399 val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr) 400 401 402 val staWaitedReleased = Cat( 403 fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value) 404 ).orR 405 val stdWaitedReleased = Cat( 406 fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value) 407 ).orR 408 val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait 409 val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd 410 val waitStd = !olderStdReady 411 val waitSta = !olderStaNotViolate 412 413 memStatusUpdate := memStatus 414 415 val shouldBlock = Mux(enqValid, commonIn.enq.bits.status.blocked, entryReg.status.blocked) 416 val blockNotReleased = waitStd || waitSta 417 entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore 418 entryRegNext.status.blocked := entryUpdate.status.blocked 419 } 420 421 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle, isEnq: Boolean, isAddr: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 422 val enqValid = if (isEnq) commonIn.enq.valid && common.enqReady 423 else commonIn.enq.valid 424 425 val fromLsq = commonIn.fromLsq.get 426 val vecMemStatus = entryReg.status.vecMem.get 427 val vecMemStatusNext = entryRegNext.status.vecMem.get 428 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 429 430 when(enqValid) { 431 vecMemStatusNext.sqIdx := commonIn.enq.bits.status.vecMem.get.sqIdx 432 vecMemStatusNext.lqIdx := commonIn.enq.bits.status.vecMem.get.lqIdx 433 }.otherwise { 434 vecMemStatusNext := vecMemStatusUpdate 435 } 436 vecMemStatusUpdate := vecMemStatus 437 438 val isLsqHead = if (isAddr) { 439 entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr && 440 entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr 441 } else { 442 entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value 443 } 444 445 entryRegNext.status.blocked := (if (isAddr) entryUpdate.status.blocked || !isLsqHead 446 else !isLsqHead) 447 } 448 449 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 450 val origExuOH = 0.U.asTypeOf(exuOH) 451 when(wakeupByIQOH.asUInt.orR) { 452 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 453 }.elsewhen(wakeup) { 454 origExuOH := 0.U.asTypeOf(origExuOH) 455 }.otherwise { 456 origExuOH := regSrcExuOH 457 } 458 exuOH := 0.U.asTypeOf(exuOH) 459 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 460 } 461 462 object IQFuType { 463 def num = FuType.num 464 465 def apply() = Vec(num, Bool()) 466 467 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 468 val res = 0.U.asTypeOf(fuType) 469 fus.foreach(x => res(x.id) := fuType(x.id)) 470 res 471 } 472 } 473} 474