1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 writeVConfig : Boolean = false, 67 writeVType : Boolean = false, 68 immType : Set[UInt] = Set(), 69 // vector 70 vconfigWakeUp : Boolean = false, 71 maskWakeUp : Boolean = false, 72) { 73 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 74 def needFpWen: Boolean = writeFpRf 75 def needVecWen: Boolean = writeVecRf 76 var vconfigIdx = -1 77 var maskSrcIdx = -1 78 if (vconfigWakeUp) { 79 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 80 } 81 if (maskWakeUp) { 82 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 83 } 84 85 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 86 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 87 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 88 89 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 93 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 94 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 95 96 def readFp: Boolean = numFpSrc > 0 97 98 def fuSel(uop: ExuInput): Bool = { 99 // Don't add more shit here!!! 100 // Todo: add new FuType to distinguish f2i, f2f 101 uop.fuType === this.fuType.U 102 } 103 104 /** 105 * params(i): data type set of the ith src port 106 * @return 107 */ 108 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 109 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 110 // make srcData is uniform sized to avoid exception when transpose 111 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 112 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 113 } 114 115 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 116 srcData 117 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 118 .filter(_.nonEmpty) 119 .map(_.get) 120 .toSet 121 } 122 123 def hasNoDataWB: Boolean = { 124 !(writeIntRf || writeFpRf || writeVecRf) 125 } 126 127 def getSrcMaxWidthVec = { 128 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 129 } 130 131 def genSrcDataVec: Seq[UInt] = { 132 getSrcMaxWidthVec.map(w => UInt(w.W)) 133 } 134 135 // csr's redirect is in its exception bundle 136 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 137 138 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 139 140 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 141 142 // predict info 143 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 144 145 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 146 147 def needFPUCtrl: Boolean = { 148 import FuType._ 149 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 150 } 151 152 def needVecCtrl: Boolean = { 153 import FuType._ 154 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 155 } 156 157 def isMul: Boolean = fuType == FuType.mul 158 159 def isDiv: Boolean = fuType == FuType.div 160 161 def isCsr: Boolean = fuType == FuType.csr 162 163 def isFence: Boolean = fuType == FuType.fence 164 165 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 166 fuType == FuType.vppu || fuType == FuType.vipu || 167 fuType == FuType.vfalu || fuType == FuType.vfma || 168 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 169 fuType == FuType.vidiv 170 171 def needOg2: Boolean = isVecArith || fuType == FuType.fmisc || fuType == FuType.vsetfwf || fuType == FuType.f2v 172 173 def isSta: Boolean = name.contains("sta") 174 175 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 176 fuType == FuType.fmisc || fuType == FuType.div || 177 fuType == FuType.vfdiv || fuType == FuType.vidiv 178 179 /** 180 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 181 * @param data [[DataConfig]] 182 * @param tips tips if get failed 183 * @return the index of special src data 184 */ 185 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 186 val srcIdxVec = srcData.map(x => x.indexOf(data)) 187 val idx0 = srcIdxVec.head 188 for (idx <- srcIdxVec) { 189 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 190 } 191 idx0 192 } 193 194 override def toString: String = { 195 var str = s"${this.name}: " 196 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 197 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 198 str += s"latency($latency)" 199 str += s"src($srcData)" 200 str 201 } 202} 203 204object FuConfig { 205 val JmpCfg: FuConfig = FuConfig ( 206 name = "jmp", 207 fuType = FuType.jmp, 208 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 209 srcData = Seq( 210 Seq(IntData()), // jal 211 ), 212 piped = true, 213 writeIntRf = true, 214 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 215 ) 216 217 val BrhCfg: FuConfig = FuConfig ( 218 name = "brh", 219 fuType = FuType.brh, 220 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 221 srcData = Seq( 222 Seq(IntData(), IntData()), 223 ), 224 piped = true, 225 immType = Set(SelImm.IMM_SB), 226 ) 227 228 val I2fCfg: FuConfig = FuConfig ( 229 name = "i2f", 230 FuType.i2f, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 232 srcData = Seq( 233 Seq(IntData()), 234 ), 235 piped = true, 236 writeFpRf = true, 237 writeFflags = true, 238 latency = CertainLatency(2), 239 needSrcFrm = true, 240 ) 241 242 val I2vCfg: FuConfig = FuConfig ( 243 name = "i2v", 244 FuType.i2v, 245 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 246 srcData = Seq( 247 Seq(IntData(), IntData()), 248 ), 249 piped = true, 250 writeVecRf = true, 251 writeFpRf = true, 252 latency = CertainLatency(0), 253 dataBits = 128, 254 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 255 ) 256 257 val F2vCfg: FuConfig = FuConfig ( 258 name = "f2v", 259 FuType.f2v, 260 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 261 srcData = Seq( 262 Seq(FpData(), FpData()), 263 Seq(FpData()), 264 ), 265 piped = true, 266 writeVecRf = true, 267 latency = CertainLatency(0), 268 dataBits = 128, 269 ) 270 271 val CsrCfg: FuConfig = FuConfig ( 272 name = "csr", 273 fuType = FuType.csr, 274 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 275 srcData = Seq( 276 Seq(IntData()), 277 ), 278 piped = true, 279 writeIntRf = true, 280 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 281 flushPipe = true, 282 ) 283 284 val AluCfg: FuConfig = FuConfig ( 285 name = "alu", 286 fuType = FuType.alu, 287 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 288 srcData = Seq( 289 Seq(IntData(), IntData()), 290 ), 291 piped = true, 292 writeIntRf = true, 293 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 294 ) 295 296 val MulCfg: FuConfig = FuConfig ( 297 name = "mul", 298 fuType = FuType.mul, 299 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 300 srcData = Seq( 301 Seq(IntData(), IntData()), 302 ), 303 piped = true, 304 writeIntRf = true, 305 latency = CertainLatency(2), 306 ) 307 308 val DivCfg: FuConfig = FuConfig ( 309 name = "div", 310 fuType = FuType.div, 311 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 312 srcData = Seq( 313 Seq(IntData(), IntData()), 314 ), 315 piped = false, 316 writeIntRf = true, 317 latency = UncertainLatency(), 318 hasInputBuffer = (true, 4, true) 319 ) 320 321 val FenceCfg: FuConfig = FuConfig ( 322 name = "fence", 323 FuType.fence, 324 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 325 srcData = Seq( 326 Seq(IntData(), IntData()), 327 ), 328 piped = true, 329 latency = CertainLatency(0), 330 exceptionOut = Seq(illegalInstr, virtualInstr), 331 flushPipe = true 332 ) 333 334 // Todo: split it to simple bitmap exu and complex bku 335 val BkuCfg: FuConfig = FuConfig ( 336 name = "bku", 337 fuType = FuType.bku, 338 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 339 srcData = Seq( 340 Seq(IntData(), IntData()), 341 ), 342 piped = true, 343 writeIntRf = true, 344 latency = CertainLatency(2), 345 ) 346 347 val VSetRvfWvfCfg: FuConfig = FuConfig( 348 name = "vsetrvfwvf", 349 fuType = FuType.vsetfwf, 350 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 351 srcData = Seq( 352 Seq(FpData(), FpData()), 353 ), 354 piped = true, 355 writeVecRf = true, 356 writeVConfig = true, 357 writeVType = true, 358 latency = CertainLatency(0), 359 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 360 ) 361 362 val VSetRiWvfCfg: FuConfig = FuConfig( 363 name = "vsetriwvf", 364 fuType = FuType.vsetiwf, 365 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 366 srcData = Seq( 367 Seq(IntData(), IntData()), 368 ), 369 piped = true, 370 writeVecRf = true, 371 writeVConfig = true, 372 writeVType = true, 373 latency = CertainLatency(0), 374 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 375 ) 376 377 val VSetRiWiCfg: FuConfig = FuConfig( 378 name = "vsetriwi", 379 fuType = FuType.vsetiwi, 380 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 381 srcData = Seq( 382 Seq(IntData(), IntData()), 383 ), 384 piped = true, 385 writeIntRf = true, 386 latency = CertainLatency(0), 387 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 388 ) 389 390 val FmacCfg: FuConfig = FuConfig ( 391 name = "fmac", 392 fuType = FuType.fmac, 393 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 394 srcData = Seq( 395 Seq(FpData(), FpData()), 396 Seq(FpData(), FpData(), FpData()), 397 ), 398 piped = false, 399 writeFpRf = true, 400 writeFflags = true, 401 latency = UncertainLatency(), 402 needSrcFrm = true, 403 ) 404 405 val F2iCfg: FuConfig = FuConfig ( 406 name = "f2i", 407 fuType = FuType.fmisc, 408 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 409 srcData = Seq( 410 Seq(FpData(), FpData()), 411 Seq(FpData()), 412 ), 413 piped = true, 414 writeIntRf = true, 415 writeFflags = true, 416 latency = CertainLatency(2), 417 needSrcFrm = true, 418 ) 419 420 val F2fCfg: FuConfig = FuConfig ( 421 name = "f2f", 422 fuType = FuType.fmisc, 423 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 424 srcData = Seq( 425 Seq(FpData(), FpData()), 426 Seq(FpData()), 427 ), 428 piped = true, 429 writeFpRf = true, 430 writeFflags = true, 431 latency = CertainLatency(2), 432 needSrcFrm = true, 433 ) 434 435 val FDivSqrtCfg: FuConfig = FuConfig ( 436 name = "fDivSqrt", 437 fuType = FuType.fDivSqrt, 438 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 439 srcData = Seq( 440 Seq(FpData(), FpData()), 441 ), 442 piped = false, 443 writeFpRf = true, 444 writeFflags = true, 445 latency = UncertainLatency(), 446 hasInputBuffer = (true, 8, true), 447 needSrcFrm = true, 448 ) 449 450 val LduCfg: FuConfig = FuConfig ( 451 name = "ldu", 452 fuType = FuType.ldu, 453 fuGen = null, // Todo 454 srcData = Seq( 455 Seq(IntData()), 456 ), 457 piped = false, // Todo: check it 458 writeIntRf = true, 459 writeFpRf = true, 460 latency = UncertainLatency(3), 461 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 462 flushPipe = true, 463 replayInst = true, 464 hasLoadError = true, 465 trigger = true, 466 immType = Set(SelImm.IMM_I), 467 ) 468 469 val StaCfg: FuConfig = FuConfig ( 470 name = "sta", 471 fuType = FuType.stu, 472 fuGen = null, // Todo 473 srcData = Seq( 474 Seq(IntData()), 475 ), 476 piped = false, 477 latency = UncertainLatency(), 478 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 479 trigger = true, 480 immType = Set(SelImm.IMM_S), 481 ) 482 483 val StdCfg: FuConfig = FuConfig ( 484 name = "std", 485 fuType = FuType.stu, 486 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 487 srcData = Seq( 488 Seq(IntData()), 489 Seq(FpData()), 490 ), 491 piped = true, 492 latency = CertainLatency(0) 493 ) 494 495 val HyldaCfg = FuConfig ( 496 name = "hylda", 497 fuType = FuType.ldu, 498 fuGen = null, // Todo 499 srcData = Seq( 500 Seq(IntData()), 501 ), 502 piped = false, // Todo: check it 503 writeIntRf = true, 504 writeFpRf = true, 505 latency = UncertainLatency(3), 506 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 507 flushPipe = true, 508 replayInst = true, 509 hasLoadError = true, 510 immType = Set(SelImm.IMM_I), 511 ) 512 513 val HystaCfg = FuConfig ( 514 name = "hysta", 515 fuType = FuType.stu, 516 fuGen = null, // Todo 517 srcData = Seq( 518 Seq(IntData()), 519 ), 520 piped = false, 521 latency = UncertainLatency(), 522 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 523 immType = Set(SelImm.IMM_S), 524 ) 525 526 val FakeHystaCfg = FuConfig ( 527 name = "hysta", 528 fuType = FuType.stu, 529 fuGen = null, // Todo 530 srcData = Seq(), 531 piped = false, 532 latency = UncertainLatency(), 533 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 534 immType = Set(), 535 ) 536 537 val MouCfg: FuConfig = FuConfig ( 538 name = "mou", 539 fuType = FuType.mou, 540 fuGen = null, // Todo 541 srcData = Seq( 542 Seq(IntData()), 543 ), 544 piped = false, // Todo: check it 545 writeFakeIntRf = true, 546 latency = UncertainLatency(), 547 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 548 trigger = true, 549 ) 550 551 val MoudCfg: FuConfig = FuConfig ( 552 name = "moud", 553 fuType = FuType.mou, 554 fuGen = null, // Todo 555 srcData = Seq( 556 Seq(IntData()), 557 ), 558 piped = true, 559 latency = CertainLatency(0), 560 ) 561 562 val VialuCfg = FuConfig ( 563 name = "vialuFix", 564 fuType = FuType.vialuF, 565 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 566 srcData = Seq( 567 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 568 ), 569 piped = true, 570 writeVecRf = true, 571 writeVxsat = true, 572 needSrcVxrm = true, 573 latency = CertainLatency(1), 574 vconfigWakeUp = true, 575 maskWakeUp = true, 576 dataBits = 128, 577 exceptionOut = Seq(illegalInstr), 578 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 579 ) 580 581 val VimacCfg = FuConfig ( 582 name = "vimac", 583 fuType = FuType.vimac, 584 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 585 srcData = Seq( 586 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 587 ), 588 piped = true, 589 writeVecRf = true, 590 writeVxsat = true, 591 needSrcVxrm = true, 592 latency = CertainLatency(2), 593 vconfigWakeUp = true, 594 maskWakeUp = true, 595 dataBits = 128, 596 exceptionOut = Seq(illegalInstr), 597 ) 598 599 val VidivCfg = FuConfig ( 600 name = "vidiv", 601 fuType = FuType.vidiv, 602 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 603 srcData = Seq( 604 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 605 ), 606 piped = false, 607 writeVecRf = true, 608 latency = UncertainLatency(), 609 vconfigWakeUp = true, 610 maskWakeUp = true, 611 dataBits = 128, 612 exceptionOut = Seq(illegalInstr), 613 ) 614 615 val VppuCfg = FuConfig ( 616 name = "vppu", 617 fuType = FuType.vppu, 618 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 619 srcData = Seq( 620 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 621 ), 622 piped = true, 623 writeVecRf = true, 624 latency = CertainLatency(2), 625 vconfigWakeUp = true, 626 maskWakeUp = true, 627 dataBits = 128, 628 exceptionOut = Seq(illegalInstr), 629 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 630 ) 631 632 val VipuCfg: FuConfig = FuConfig ( 633 name = "vipu", 634 fuType = FuType.vipu, 635 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 636 srcData = Seq( 637 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 638 ), 639 piped = true, 640 writeIntRf = true, 641 writeVecRf = true, 642 latency = CertainLatency(2), 643 vconfigWakeUp = true, 644 maskWakeUp = true, 645 dataBits = 128, 646 exceptionOut = Seq(illegalInstr), 647 ) 648 649 val VfaluCfg = FuConfig ( 650 name = "vfalu", 651 fuType = FuType.vfalu, 652 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 653 srcData = Seq( 654 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 655 ), 656 piped = true, 657 writeVecRf = true, 658 writeFpRf = true, 659 writeIntRf = true, 660 writeFflags = true, 661 latency = CertainLatency(1), 662 vconfigWakeUp = true, 663 maskWakeUp = true, 664 dataBits = 128, 665 exceptionOut = Seq(illegalInstr), 666 needSrcFrm = true, 667 ) 668 669 val VfmaCfg = FuConfig ( 670 name = "vfma", 671 fuType = FuType.vfma, 672 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 673 srcData = Seq( 674 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 675 ), 676 piped = true, 677 writeVecRf = true, 678 writeFpRf = true, 679 writeFflags = true, 680 latency = CertainLatency(3), 681 vconfigWakeUp = true, 682 maskWakeUp = true, 683 dataBits = 128, 684 exceptionOut = Seq(illegalInstr), 685 needSrcFrm = true, 686 ) 687 688 val VfdivCfg = FuConfig( 689 name = "vfdiv", 690 fuType = FuType.vfdiv, 691 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 692 srcData = Seq( 693 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 694 ), 695 piped = false, 696 writeVecRf = true, 697 writeFpRf = true, 698 writeFflags = true, 699 latency = UncertainLatency(), 700 vconfigWakeUp = true, 701 maskWakeUp = true, 702 dataBits = 128, 703 exceptionOut = Seq(illegalInstr), 704 needSrcFrm = true, 705 ) 706 707 val VfcvtCfg = FuConfig( 708 name = "vfcvt", 709 fuType = FuType.vfcvt, 710 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 711 srcData = Seq( 712 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 713 ), 714 piped = true, 715 writeVecRf = true, 716 writeFpRf = true, 717 writeIntRf = true, 718 writeFflags = true, 719 latency = CertainLatency(2), 720 vconfigWakeUp = true, 721 maskWakeUp = true, 722 dataBits = 128, 723 exceptionOut = Seq(illegalInstr), 724 needSrcFrm = true, 725 ) 726 727 728 val VlduCfg: FuConfig = FuConfig ( 729 name = "vldu", 730 fuType = FuType.vldu, 731 fuGen = null, 732 srcData = Seq( 733 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 734 ), 735 piped = false, // Todo: check it 736 writeVecRf = true, 737 latency = UncertainLatency(), 738 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 739 flushPipe = true, 740 replayInst = true, 741 hasLoadError = true, 742 vconfigWakeUp = true, 743 maskWakeUp = true, 744 dataBits = 128, 745 ) 746 747 val VstuCfg: FuConfig = FuConfig ( 748 name = "vstu", 749 fuType = FuType.vstu, 750 fuGen = null, 751 srcData = Seq( 752 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 753 ), 754 piped = false, 755 writeVecRf = false, 756 latency = UncertainLatency(), 757 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 758 flushPipe = true, 759 replayInst = true, 760 hasLoadError = true, 761 vconfigWakeUp = true, 762 maskWakeUp = true, 763 dataBits = 128, 764 ) 765 766 def allConfigs = Seq( 767 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 768 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 769 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 770 ) 771 772 def VecArithFuConfigs = Seq( 773 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 774 ) 775} 776 777