1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.{max, min} 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HSXLEN: Int = 64, 63 HasMExtension: Boolean = true, 64 HasCExtension: Boolean = true, 65 HasHExtension: Boolean = true, 66 HasDiv: Boolean = true, 67 HasICache: Boolean = true, 68 HasDCache: Boolean = true, 69 AddrBits: Int = 64, 70 VAddrBits: Int = 39, 71 GPAddrBits: Int = 41, 72 HasFPU: Boolean = true, 73 HasVPU: Boolean = true, 74 HasCustomCSRCacheOp: Boolean = true, 75 FetchWidth: Int = 8, 76 AsidLength: Int = 16, 77 VmidLength: Int = 14, 78 EnableBPU: Boolean = true, 79 EnableBPD: Boolean = true, 80 EnableRAS: Boolean = true, 81 EnableLB: Boolean = false, 82 EnableLoop: Boolean = true, 83 EnableSC: Boolean = true, 84 EnbaleTlbDebug: Boolean = false, 85 EnableClockGate: Boolean = true, 86 EnableJal: Boolean = false, 87 EnableFauFTB: Boolean = true, 88 UbtbGHRLength: Int = 4, 89 // HistoryLength: Int = 512, 90 EnableGHistDiff: Boolean = true, 91 EnableCommitGHistDiff: Boolean = true, 92 UbtbSize: Int = 256, 93 FtbSize: Int = 2048, 94 RasSize: Int = 16, 95 RasSpecSize: Int = 32, 96 RasCtrSize: Int = 3, 97 CacheLineSize: Int = 512, 98 FtbWays: Int = 4, 99 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 100 // Sets Hist Tag 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 118 (resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val uftb = Module(new FauFTB()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(uftb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 128 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 129 130 uftb.io.in.bits.resp_in(0) := resp_in 131 tage.io.in.bits.resp_in(0) := uftb.io.out 132 ftb.io.in.bits.resp_in(0) := tage.io.out 133 ittage.io.in.bits.resp_in(0) := ftb.io.out 134 ras.io.in.bits.resp_in(0) := ittage.io.out 135 136 (preds, ras.io.out) 137 }, 138 ICacheForceMetaECCError: Boolean = false, 139 ICacheForceDataECCError: Boolean = false, 140 IBufSize: Int = 48, 141 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 8, 145 RobCommitWidth: Int = 8, 146 RabCommitWidth: Int = 6, 147 MaxUopSize: Int = 65, 148 EnableRenameSnapshot: Boolean = true, 149 RenameSnapshotNum: Int = 4, 150 FtqSize: Int = 64, 151 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 152 IntLogicRegs: Int = 32, 153 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 154 VecLogicRegs: Int = 32 + 15, // 15: tmp 155 V0LogicRegs: Int = 1, // V0 156 VlLogicRegs: Int = 1, // Vl 157 V0_IDX: Int = 0, 158 Vl_IDX: Int = 0, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 8, 181 FpDqDeqWidth = 6, 182 VecDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 fpPreg: PregParams = FpPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 vfPreg: VfPregParams = VfPregParams( 196 numEntries = 128, 197 numRead = None, 198 numWrite = None, 199 ), 200 v0Preg: V0PregParams = V0PregParams( 201 numEntries = 22, 202 numRead = None, 203 numWrite = None, 204 ), 205 vlPreg: VlPregParams = VlPregParams( 206 numEntries = 32, 207 numRead = None, 208 numWrite = None, 209 ), 210 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 211 LoadPipelineWidth: Int = 3, 212 StorePipelineWidth: Int = 2, 213 VecLoadPipelineWidth: Int = 2, 214 VecStorePipelineWidth: Int = 2, 215 VecMemSrcInWidth: Int = 2, 216 VecMemInstWbWidth: Int = 1, 217 VecMemDispatchWidth: Int = 1, 218 VecMemDispatchMaxNumber: Int = 16, 219 VecMemUnitStrideMaxFlowNum: Int = 2, 220 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 221 StoreBufferSize: Int = 16, 222 StoreBufferThreshold: Int = 7, 223 EnsbufferWidth: Int = 2, 224 LoadDependencyWidth: Int = 2, 225 // ============ VLSU ============ 226 VlMergeBufferSize: Int = 16, 227 VsMergeBufferSize: Int = 16, 228 UopWritebackWidth: Int = 2, 229 VLUopWritebackWidth: Int = 2, 230 VSUopWritebackWidth: Int = 1, 231 VSegmentBufferSize: Int = 8, 232 // ============================== 233 UncacheBufferSize: Int = 4, 234 EnableLoadToLoadForward: Boolean = false, 235 EnableFastForward: Boolean = true, 236 EnableLdVioCheckAfterReset: Boolean = true, 237 EnableSoftPrefetchAfterReset: Boolean = true, 238 EnableCacheErrorAfterReset: Boolean = true, 239 EnableAccurateLoadError: Boolean = false, 240 EnableUncacheWriteOutstanding: Boolean = false, 241 EnableStorePrefetchAtIssue: Boolean = false, 242 EnableStorePrefetchAtCommit: Boolean = false, 243 EnableAtCommitMissTrigger: Boolean = true, 244 EnableStorePrefetchSMS: Boolean = false, 245 EnableStorePrefetchSPB: Boolean = false, 246 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 247 MMUVmidLen: Int = 14, 248 ReSelectLen: Int = 7, // load replay queue replay select counter len 249 iwpuParameters: WPUParameters = WPUParameters( 250 enWPU = false, 251 algoName = "mmru", 252 isICache = true, 253 ), 254 dwpuParameters: WPUParameters = WPUParameters( 255 enWPU = false, 256 algoName = "mmru", 257 enCfPred = false, 258 isICache = false, 259 ), 260 itlbParameters: TLBParameters = TLBParameters( 261 name = "itlb", 262 fetchi = true, 263 useDmode = false, 264 NWays = 48, 265 ), 266 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 267 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 268 ldtlbParameters: TLBParameters = TLBParameters( 269 name = "ldtlb", 270 NWays = 48, 271 outReplace = false, 272 partialStaticPMP = true, 273 outsideRecvFlush = true, 274 saveLevel = true, 275 lgMaxSize = 4 276 ), 277 sttlbParameters: TLBParameters = TLBParameters( 278 name = "sttlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = true, 284 lgMaxSize = 4 285 ), 286 hytlbParameters: TLBParameters = TLBParameters( 287 name = "hytlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = true, 293 lgMaxSize = 4 294 ), 295 pftlbParameters: TLBParameters = TLBParameters( 296 name = "pftlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = true, 302 lgMaxSize = 4 303 ), 304 l2ToL1tlbParameters: TLBParameters = TLBParameters( 305 name = "l2tlb", 306 NWays = 48, 307 outReplace = false, 308 partialStaticPMP = true, 309 outsideRecvFlush = true, 310 saveLevel = true 311 ), 312 refillBothTlb: Boolean = false, 313 btlbParameters: TLBParameters = TLBParameters( 314 name = "btlb", 315 NWays = 48, 316 ), 317 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 318 NumPerfCounters: Int = 16, 319 icacheParameters: ICacheParameters = ICacheParameters( 320 tagECC = Some("parity"), 321 dataECC = Some("parity"), 322 replacer = Some("setplru"), 323 ), 324 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 325 tagECC = Some("secded"), 326 dataECC = Some("secded"), 327 replacer = Some("setplru"), 328 nMissEntries = 16, 329 nProbeEntries = 8, 330 nReleaseEntries = 18, 331 nMaxPrefetchEntry = 6, 332 )), 333 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 334 name = "l2", 335 ways = 8, 336 sets = 1024, // default 512KB L2 337 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 338 coupledL2.prefetch.TPParameters()), 339 )), 340 L2NBanks: Int = 1, 341 usePTWRepeater: Boolean = false, 342 softTLB: Boolean = false, // dpi-c l1tlb debug only 343 softPTW: Boolean = false, // dpi-c l2tlb debug only 344 softPTWDelay: Int = 1 345){ 346 def vlWidth = log2Up(VLEN) + 1 347 348 /** 349 * the minimum element length of vector elements 350 */ 351 val minVecElen: Int = 8 352 353 /** 354 * the maximum number of elements in vector register 355 */ 356 val maxElemPerVreg: Int = VLEN / minVecElen 357 358 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 359 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 360 361 val intSchdParams = { 362 implicit val schdType: SchedulerType = IntScheduler() 363 SchdBlockParams(Seq( 364 IssueBlockParams(Seq( 365 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 366 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 367 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 368 IssueBlockParams(Seq( 369 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 370 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 371 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 372 IssueBlockParams(Seq( 373 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 374 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 375 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 376 IssueBlockParams(Seq( 377 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 378 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 379 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 380 ), 381 numPregs = intPreg.numEntries, 382 numDeqOutside = 0, 383 schdType = schdType, 384 rfDataWidth = intPreg.dataCfg.dataWidth, 385 numUopIn = dpParams.IntDqDeqWidth, 386 ) 387 } 388 389 val fpSchdParams = { 390 implicit val schdType: SchedulerType = FpScheduler() 391 SchdBlockParams(Seq( 392 IssueBlockParams(Seq( 393 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 394 ), numEntries = 18, numEnq = 2, numComp = 16), 395 IssueBlockParams(Seq( 396 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 397 ), numEntries = 18, numEnq = 2, numComp = 16), 398 IssueBlockParams(Seq( 399 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 400 ), numEntries = 18, numEnq = 2, numComp = 16), 401 IssueBlockParams(Seq( 402 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 403 ), numEntries = 18, numEnq = 2, numComp = 16), 404 IssueBlockParams(Seq( 405 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 406 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 407 ), numEntries = 18, numEnq = 2, numComp = 16), 408 ), 409 numPregs = fpPreg.numEntries, 410 numDeqOutside = 0, 411 schdType = schdType, 412 rfDataWidth = fpPreg.dataCfg.dataWidth, 413 numUopIn = dpParams.VecDqDeqWidth, 414 ) 415 } 416 417 val vfSchdParams = { 418 implicit val schdType: SchedulerType = VfScheduler() 419 SchdBlockParams(Seq( 420 IssueBlockParams(Seq( 421 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 422 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 423 ), numEntries = 16, numEnq = 2, numComp = 14), 424 IssueBlockParams(Seq( 425 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 426 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 427 ), numEntries = 16, numEnq = 2, numComp = 14), 428 IssueBlockParams(Seq( 429 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 430 ), numEntries = 10, numEnq = 2, numComp = 8), 431 ), 432 numPregs = vfPreg.numEntries, 433 numDeqOutside = 0, 434 schdType = schdType, 435 rfDataWidth = vfPreg.dataCfg.dataWidth, 436 numUopIn = dpParams.VecDqDeqWidth, 437 ) 438 } 439 440 val memSchdParams = { 441 implicit val schdType: SchedulerType = MemScheduler() 442 val rfDataWidth = 64 443 444 SchdBlockParams(Seq( 445 IssueBlockParams(Seq( 446 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 447 ), numEntries = 16, numEnq = 2, numComp = 14), 448 IssueBlockParams(Seq( 449 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 450 ), numEntries = 16, numEnq = 2, numComp = 14), 451 IssueBlockParams(Seq( 452 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 453 ), numEntries = 16, numEnq = 2, numComp = 14), 454 IssueBlockParams(Seq( 455 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 456 ), numEntries = 16, numEnq = 2, numComp = 14), 457 IssueBlockParams(Seq( 458 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 459 ), numEntries = 16, numEnq = 2, numComp = 14), 460 IssueBlockParams(Seq( 461 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 462 ), numEntries = 16, numEnq = 2, numComp = 14), 463 IssueBlockParams(Seq( 464 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 465 ), numEntries = 16, numEnq = 2, numComp = 14), 466 IssueBlockParams(Seq( 467 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 468 ), numEntries = 16, numEnq = 2, numComp = 14), 469 IssueBlockParams(Seq( 470 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 471 ), numEntries = 16, numEnq = 2, numComp = 14), 472 ), 473 numPregs = intPreg.numEntries max vfPreg.numEntries, 474 numDeqOutside = 0, 475 schdType = schdType, 476 rfDataWidth = rfDataWidth, 477 numUopIn = dpParams.LsDqDeqWidth, 478 ) 479 } 480 481 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 482 483 def iqWakeUpParams = { 484 Seq( 485 WakeUpConfig( 486 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 487 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 488 ), 489 WakeUpConfig( 490 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 491 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 492 ), 493 WakeUpConfig( 494 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 495 Seq("STD0", "STD1") 496 ), 497// WakeUpConfig( 498// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 499// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 500// ), 501 ).flatten 502 } 503 504 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 505 506 val backendParams: BackendParams = backend.BackendParams( 507 Map( 508 IntScheduler() -> intSchdParams, 509 FpScheduler() -> fpSchdParams, 510 VfScheduler() -> vfSchdParams, 511 MemScheduler() -> memSchdParams, 512 ), 513 Seq( 514 intPreg, 515 fpPreg, 516 vfPreg, 517 v0Preg, 518 vlPreg, 519 fakeIntPreg 520 ), 521 iqWakeUpParams, 522 ) 523} 524 525case object DebugOptionsKey extends Field[DebugOptions] 526 527case class DebugOptions 528( 529 FPGAPlatform: Boolean = false, 530 ResetGen: Boolean = false, 531 EnableDifftest: Boolean = false, 532 AlwaysBasicDiff: Boolean = true, 533 EnableDebug: Boolean = false, 534 EnablePerfDebug: Boolean = true, 535 UseDRAMSim: Boolean = false, 536 EnableConstantin: Boolean = false, 537 EnableChiselDB: Boolean = false, 538 AlwaysBasicDB: Boolean = true, 539 EnableRollingDB: Boolean = false 540) 541 542trait HasXSParameter { 543 544 implicit val p: Parameters 545 546 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 547 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 548 549 def coreParams = p(XSCoreParamsKey) 550 def env = p(DebugOptionsKey) 551 552 def XLEN = coreParams.XLEN 553 def VLEN = coreParams.VLEN 554 def ELEN = coreParams.ELEN 555 def HSXLEN = coreParams.HSXLEN 556 val minFLen = 32 557 val fLen = 64 558 def hartIdLen = p(MaxHartIdBits) 559 val xLen = XLEN 560 561 def HasMExtension = coreParams.HasMExtension 562 def HasCExtension = coreParams.HasCExtension 563 def HasHExtension = coreParams.HasHExtension 564 def HasDiv = coreParams.HasDiv 565 def HasIcache = coreParams.HasICache 566 def HasDcache = coreParams.HasDCache 567 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 568 def GPAddrBits = coreParams.GPAddrBits 569 def VAddrBits = { 570 if(HasHExtension){ 571 coreParams.GPAddrBits 572 }else{ 573 coreParams.VAddrBits 574 } 575 } // VAddrBits is Virtual Memory addr bits 576 577 def AsidLength = coreParams.AsidLength 578 def VmidLength = coreParams.VmidLength 579 def ReSelectLen = coreParams.ReSelectLen 580 def AddrBytes = AddrBits / 8 // unused 581 def DataBits = XLEN 582 def DataBytes = DataBits / 8 583 def VDataBytes = VLEN / 8 584 def HasFPU = coreParams.HasFPU 585 def HasVPU = coreParams.HasVPU 586 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 587 def FetchWidth = coreParams.FetchWidth 588 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 589 def EnableBPU = coreParams.EnableBPU 590 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 591 def EnableRAS = coreParams.EnableRAS 592 def EnableLB = coreParams.EnableLB 593 def EnableLoop = coreParams.EnableLoop 594 def EnableSC = coreParams.EnableSC 595 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 596 def HistoryLength = coreParams.HistoryLength 597 def EnableGHistDiff = coreParams.EnableGHistDiff 598 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 599 def EnableClockGate = coreParams.EnableClockGate 600 def UbtbGHRLength = coreParams.UbtbGHRLength 601 def UbtbSize = coreParams.UbtbSize 602 def EnableFauFTB = coreParams.EnableFauFTB 603 def FtbSize = coreParams.FtbSize 604 def FtbWays = coreParams.FtbWays 605 def RasSize = coreParams.RasSize 606 def RasSpecSize = coreParams.RasSpecSize 607 def RasCtrSize = coreParams.RasCtrSize 608 609 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 610 coreParams.branchPredictor(resp_in, p) 611 } 612 def numBr = coreParams.numBr 613 def TageTableInfos = coreParams.TageTableInfos 614 def TageBanks = coreParams.numBr 615 def SCNRows = coreParams.SCNRows 616 def SCCtrBits = coreParams.SCCtrBits 617 def SCHistLens = coreParams.SCHistLens 618 def SCNTables = coreParams.SCNTables 619 620 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 621 case ((n, cb), h) => (n, cb, h) 622 } 623 def ITTageTableInfos = coreParams.ITTageTableInfos 624 type FoldedHistoryInfo = Tuple2[Int, Int] 625 def foldedGHistInfos = 626 (TageTableInfos.map{ case (nRows, h, t) => 627 if (h > 0) 628 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 629 else 630 Set[FoldedHistoryInfo]() 631 }.reduce(_++_).toSet ++ 632 SCTableInfos.map{ case (nRows, _, h) => 633 if (h > 0) 634 Set((h, min(log2Ceil(nRows/TageBanks), h))) 635 else 636 Set[FoldedHistoryInfo]() 637 }.reduce(_++_).toSet ++ 638 ITTageTableInfos.map{ case (nRows, h, t) => 639 if (h > 0) 640 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 641 else 642 Set[FoldedHistoryInfo]() 643 }.reduce(_++_) ++ 644 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 645 ).toList 646 647 648 649 def CacheLineSize = coreParams.CacheLineSize 650 def CacheLineHalfWord = CacheLineSize / 16 651 def ExtHistoryLength = HistoryLength + 64 652 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 653 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 654 def IBufSize = coreParams.IBufSize 655 def IBufNBank = coreParams.IBufNBank 656 def backendParams: BackendParams = coreParams.backendParams 657 def DecodeWidth = coreParams.DecodeWidth 658 def RenameWidth = coreParams.RenameWidth 659 def CommitWidth = coreParams.CommitWidth 660 def RobCommitWidth = coreParams.RobCommitWidth 661 def RabCommitWidth = coreParams.RabCommitWidth 662 def MaxUopSize = coreParams.MaxUopSize 663 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 664 def RenameSnapshotNum = coreParams.RenameSnapshotNum 665 def FtqSize = coreParams.FtqSize 666 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 667 def IntLogicRegs = coreParams.IntLogicRegs 668 def FpLogicRegs = coreParams.FpLogicRegs 669 def VecLogicRegs = coreParams.VecLogicRegs 670 def V0LogicRegs = coreParams.V0LogicRegs 671 def VlLogicRegs = coreParams.VlLogicRegs 672 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 673 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 674 def V0_IDX = coreParams.V0_IDX 675 def Vl_IDX = coreParams.Vl_IDX 676 def IntPhyRegs = coreParams.intPreg.numEntries 677 def FpPhyRegs = coreParams.fpPreg.numEntries 678 def VfPhyRegs = coreParams.vfPreg.numEntries 679 def V0PhyRegs = coreParams.v0Preg.numEntries 680 def VlPhyRegs = coreParams.vlPreg.numEntries 681 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 682 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 683 def RobSize = coreParams.RobSize 684 def RabSize = coreParams.RabSize 685 def VTypeBufferSize = coreParams.VTypeBufferSize 686 /** 687 * the minimum element length of vector elements 688 */ 689 def minVecElen: Int = coreParams.minVecElen 690 691 /** 692 * the maximum number of elements in vector register 693 */ 694 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 695 696 def IntRefCounterWidth = log2Ceil(RobSize) 697 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 698 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 699 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 700 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 701 def LoadQueueRARSize = coreParams.LoadQueueRARSize 702 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 703 def RollbackGroupSize = coreParams.RollbackGroupSize 704 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 705 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 706 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 707 def StoreQueueSize = coreParams.StoreQueueSize 708 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 709 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 710 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 711 def VlsQueueSize = coreParams.VlsQueueSize 712 def dpParams = coreParams.dpParams 713 714 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 715 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 716 717 def NumRedirect = backendParams.numRedirect 718 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 719 def FtqRedirectAheadNum = NumRedirect 720 def LoadPipelineWidth = coreParams.LoadPipelineWidth 721 def StorePipelineWidth = coreParams.StorePipelineWidth 722 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 723 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 724 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 725 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 726 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 727 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 728 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 729 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 730 def StoreBufferSize = coreParams.StoreBufferSize 731 def StoreBufferThreshold = coreParams.StoreBufferThreshold 732 def EnsbufferWidth = coreParams.EnsbufferWidth 733 def LoadDependencyWidth = coreParams.LoadDependencyWidth 734 def VlMergeBufferSize = coreParams.VlMergeBufferSize 735 def VsMergeBufferSize = coreParams.VsMergeBufferSize 736 def UopWritebackWidth = coreParams.UopWritebackWidth 737 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 738 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 739 def VSegmentBufferSize = coreParams.VSegmentBufferSize 740 def UncacheBufferSize = coreParams.UncacheBufferSize 741 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 742 def EnableFastForward = coreParams.EnableFastForward 743 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 744 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 745 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 746 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 747 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 748 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 749 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 750 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 751 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 752 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 753 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 754 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 755 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 756 def asidLen = coreParams.MMUAsidLen 757 def vmidLen = coreParams.MMUVmidLen 758 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 759 def refillBothTlb = coreParams.refillBothTlb 760 def iwpuParam = coreParams.iwpuParameters 761 def dwpuParam = coreParams.dwpuParameters 762 def itlbParams = coreParams.itlbParameters 763 def ldtlbParams = coreParams.ldtlbParameters 764 def sttlbParams = coreParams.sttlbParameters 765 def hytlbParams = coreParams.hytlbParameters 766 def pftlbParams = coreParams.pftlbParameters 767 def l2ToL1Params = coreParams.l2ToL1tlbParameters 768 def btlbParams = coreParams.btlbParameters 769 def l2tlbParams = coreParams.l2tlbParameters 770 def NumPerfCounters = coreParams.NumPerfCounters 771 772 def instBytes = if (HasCExtension) 2 else 4 773 def instOffsetBits = log2Ceil(instBytes) 774 775 def icacheParameters = coreParams.icacheParameters 776 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 777 778 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 779 // for constrained LR/SC loop 780 def LRSCCycles = 64 781 // for lr storm 782 def LRSCBackOff = 8 783 784 // cache hierarchy configurations 785 def l1BusDataWidth = 256 786 787 // load violation predict 788 def ResetTimeMax2Pow = 20 //1078576 789 def ResetTimeMin2Pow = 10 //1024 790 // wait table parameters 791 def WaitTableSize = 1024 792 def MemPredPCWidth = log2Up(WaitTableSize) 793 def LWTUse2BitCounter = true 794 // store set parameters 795 def SSITSize = WaitTableSize 796 def LFSTSize = 32 797 def SSIDWidth = log2Up(LFSTSize) 798 def LFSTWidth = 4 799 def StoreSetEnable = true // LWT will be disabled if SS is enabled 800 def LFSTEnable = true 801 802 def PCntIncrStep: Int = 6 803 def numPCntHc: Int = 25 804 def numPCntPtw: Int = 19 805 806 def numCSRPCntFrontend = 8 807 def numCSRPCntCtrl = 8 808 def numCSRPCntLsu = 8 809 def numCSRPCntHc = 5 810 def printEventCoding = true 811 812 // Parameters for Sdtrig extension 813 protected def TriggerNum = 4 814 protected def TriggerChainMaxLength = 2 815} 816