xref: /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala (revision 395c8649bcb60eb5e4d04db942257de206b00975) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17// See LICENSE.Berkeley for license details.
18// See LICENSE.SiFive for license details.
19
20package xiangshan.backend.fu.fpu
21
22import org.chipsalliance.cde.config.Parameters
23import chisel3._
24import chisel3.util._
25import utility.{SignExt, ZeroExt}
26import xiangshan.backend.fu.{FuConfig, FuncUnit, PipedFuncUnit}
27import xiangshan.backend.fu.vector.Bundles.VSew
28import xiangshan.IF2VectorType
29
30class IntFPToVec(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cfg) {
31  protected val in = io.in.bits
32  protected val out = io.out.bits
33
34  // vsew is the lowest 2 bits of fuOpType
35  private val isImm = IF2VectorType.isImm(in.ctrl.fuOpType(4, 2))
36  // when needDup is true, the scalar data is duplicated in vector register
37  private val needDup = IF2VectorType.needDup(in.ctrl.fuOpType(4, 2))
38
39  // imm use src(1), scalar use src(0)
40  private val scalaData = Mux(isImm, in.data.src(1), in.data.src(0))
41  // vsew is the lowest 2 bits of fuOpType
42  private val vsew = in.ctrl.fuOpType(1, 0)
43  private val dataWidth = cfg.dataBits
44
45  private val vecE8Data  = Wire(Vec(dataWidth /  8, UInt( 8.W)))
46  private val vecE16Data = Wire(Vec(dataWidth / 16, UInt(16.W)))
47  private val vecE32Data = Wire(Vec(dataWidth / 32, UInt(32.W)))
48  private val vecE64Data = Wire(Vec(dataWidth / 64, UInt(64.W)))
49
50  vecE8Data   := VecInit(Seq.fill(dataWidth /  8)(scalaData( 7, 0)))
51  vecE16Data  := VecInit(Seq.fill(dataWidth / 16)(scalaData(15, 0)))
52  vecE32Data  := VecInit(Seq.fill(dataWidth / 32)(scalaData(31, 0)))
53  vecE64Data  := VecInit(Seq.fill(dataWidth / 64)(scalaData(63, 0)))
54
55  out.res.data := Mux(needDup, Mux1H(Seq(
56    (vsew === VSew.e8)  -> vecE8Data.asUInt,
57    (vsew === VSew.e16) -> vecE16Data.asUInt,
58    (vsew === VSew.e32) -> vecE32Data.asUInt,
59    (vsew === VSew.e64) -> vecE64Data.asUInt,
60  )), scalaData)
61}
62