| #
20b2b626 |
| 26-Aug-2024 |
sinceforYy <[email protected]> |
feat(riscv64): Support RISC-V Zfa extension
* Support fli.{h.s.d}, fminm.{h.s.d}, fmaxm.{h.s.d}
* Support fround.{h.s.d}, froundnx.{h.s.d}, fcvtmod.w.d
* Support fleq.{h.s.d}, fltq.{h.s.d}
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| #
2d12882c |
| 09-Jun-2024 |
xiaofeibao <[email protected]> |
FuConfig: split dataBits into destDataBits and srcDataBits for distinguish input and output data width
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| #
db7becb6 |
| 30-May-2024 |
xiaofeibao <[email protected]> |
Exu: connect V0Wen VlWen
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| #
5820cff8 |
| 05-Jun-2024 |
lewislzh <[email protected]> |
FPU: fix f2v boxing error when higher bits are not all zeros (#3035)
FPU: fix f2v boxing error
set result as NAN when higher bit are not all zeros
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| #
23ea5b5e |
| 20-Mar-2024 |
Ziyue Zhang <[email protected]> |
rv64v: replace all i2f move instructions to i2v instructions
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| #
395c8649 |
| 04-Jan-2024 |
Ziyue-Zhang <[email protected]> |
rv64v: add f2v to remove all fs1 duplicate logic (#2613)
* rv64v: add f2v to remove all fs1 duplicate logic
* rv64v: use IntFPToVec module for i2v and f2v
|