1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableClockGate: Boolean = true, 82 EnableJal: Boolean = false, 83 EnableFauFTB: Boolean = true, 84 UbtbGHRLength: Int = 4, 85 // HistoryLength: Int = 512, 86 EnableGHistDiff: Boolean = true, 87 EnableCommitGHistDiff: Boolean = true, 88 UbtbSize: Int = 256, 89 FtbSize: Int = 2048, 90 RasSize: Int = 16, 91 RasSpecSize: Int = 32, 92 RasCtrSize: Int = 3, 93 CacheLineSize: Int = 512, 94 FtbWays: Int = 4, 95 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 // Seq(( 2048, 2, 8), 98 // ( 2048, 9, 8), 99 // ( 2048, 13, 8), 100 // ( 2048, 20, 8), 101 // ( 2048, 26, 8), 102 // ( 2048, 44, 8), 103 // ( 2048, 73, 8), 104 // ( 2048, 256, 8)), 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 122 ((resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val ubtb =Module(new FauFTB()(p)) 125 // val bim = Module(new BIM()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(ubtb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 // ubtb.io.resp_in(0) := resp_in 133 // bim.io.resp_in(0) := ubtb.io.resp 134 // btb.io.resp_in(0) := bim.io.resp 135 // tage.io.resp_in(0) := btb.io.resp 136 // loop.io.resp_in(0) := tage.io.resp 137 ubtb.io.in.bits.resp_in(0) := resp_in 138 tage.io.in.bits.resp_in(0) := ubtb.io.out 139 ftb.io.in.bits.resp_in(0) := tage.io.out 140 ittage.io.in.bits.resp_in(0) := ftb.io.out 141 ras.io.in.bits.resp_in(0) := ittage.io.out 142 143 (preds, ras.io.out) 144 }), 145 ICacheECCForceError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 159 VCONFIG_IDX: Int = 32, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 vfPreg: VfPregParams = VfPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 196 LoadPipelineWidth: Int = 3, 197 StorePipelineWidth: Int = 2, 198 VecLoadPipelineWidth: Int = 3, 199 VecStorePipelineWidth: Int = 2, 200 VecMemSrcInWidth: Int = 2, 201 VecMemInstWbWidth: Int = 1, 202 VecMemDispatchWidth: Int = 1, 203 StoreBufferSize: Int = 16, 204 StoreBufferThreshold: Int = 7, 205 EnsbufferWidth: Int = 2, 206 // ============ VLSU ============ 207 VlMergeBufferSize: Int = 8, 208 VsMergeBufferSize: Int = 8, 209 UopWritebackWidth: Int = 1, 210 SplitBufferSize: Int = 8, 211 // ============================== 212 UncacheBufferSize: Int = 4, 213 EnableLoadToLoadForward: Boolean = false, 214 EnableFastForward: Boolean = true, 215 EnableLdVioCheckAfterReset: Boolean = true, 216 EnableSoftPrefetchAfterReset: Boolean = true, 217 EnableCacheErrorAfterReset: Boolean = true, 218 EnableAccurateLoadError: Boolean = true, 219 EnableUncacheWriteOutstanding: Boolean = false, 220 EnableStorePrefetchAtIssue: Boolean = false, 221 EnableStorePrefetchAtCommit: Boolean = false, 222 EnableAtCommitMissTrigger: Boolean = true, 223 EnableStorePrefetchSMS: Boolean = false, 224 EnableStorePrefetchSPB: Boolean = false, 225 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 226 ReSelectLen: Int = 7, // load replay queue replay select counter len 227 iwpuParameters: WPUParameters = WPUParameters( 228 enWPU = false, 229 algoName = "mmru", 230 isICache = true, 231 ), 232 dwpuParameters: WPUParameters = WPUParameters( 233 enWPU = false, 234 algoName = "mmru", 235 enCfPred = false, 236 isICache = false, 237 ), 238 itlbParameters: TLBParameters = TLBParameters( 239 name = "itlb", 240 fetchi = true, 241 useDmode = false, 242 NWays = 48, 243 ), 244 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 245 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 246 ldtlbParameters: TLBParameters = TLBParameters( 247 name = "ldtlb", 248 NWays = 48, 249 outReplace = false, 250 partialStaticPMP = true, 251 outsideRecvFlush = true, 252 saveLevel = true, 253 lgMaxSize = 4 254 ), 255 sttlbParameters: TLBParameters = TLBParameters( 256 name = "sttlb", 257 NWays = 48, 258 outReplace = false, 259 partialStaticPMP = true, 260 outsideRecvFlush = true, 261 saveLevel = true, 262 lgMaxSize = 4 263 ), 264 hytlbParameters: TLBParameters = TLBParameters( 265 name = "hytlb", 266 NWays = 48, 267 outReplace = false, 268 partialStaticPMP = true, 269 outsideRecvFlush = true, 270 saveLevel = true, 271 lgMaxSize = 4 272 ), 273 pftlbParameters: TLBParameters = TLBParameters( 274 name = "pftlb", 275 NWays = 48, 276 outReplace = false, 277 partialStaticPMP = true, 278 outsideRecvFlush = true, 279 saveLevel = true, 280 lgMaxSize = 4 281 ), 282 refillBothTlb: Boolean = false, 283 btlbParameters: TLBParameters = TLBParameters( 284 name = "btlb", 285 NWays = 48, 286 ), 287 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 288 NumPerfCounters: Int = 16, 289 icacheParameters: ICacheParameters = ICacheParameters( 290 tagECC = Some("parity"), 291 dataECC = Some("parity"), 292 replacer = Some("setplru"), 293 nMissEntries = 2, 294 nProbeEntries = 2, 295 nPrefetchEntries = 12, 296 nPrefBufferEntries = 32, 297 ), 298 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 299 tagECC = Some("secded"), 300 dataECC = Some("secded"), 301 replacer = Some("setplru"), 302 nMissEntries = 16, 303 nProbeEntries = 8, 304 nReleaseEntries = 18, 305 nMaxPrefetchEntry = 6, 306 )), 307 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 308 name = "l2", 309 ways = 8, 310 sets = 1024, // default 512KB L2 311 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 312 )), 313 L2NBanks: Int = 1, 314 usePTWRepeater: Boolean = false, 315 softTLB: Boolean = false, // dpi-c l1tlb debug only 316 softPTW: Boolean = false, // dpi-c l2tlb debug only 317 softPTWDelay: Int = 1 318){ 319 def vlWidth = log2Up(VLEN) + 1 320 321 /** 322 * the minimum element length of vector elements 323 */ 324 val minVecElen: Int = 8 325 326 /** 327 * the maximum number of elements in vector register 328 */ 329 val maxElemPerVreg: Int = VLEN / minVecElen 330 331 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 332 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 333 334 val intSchdParams = { 335 implicit val schdType: SchedulerType = IntScheduler() 336 SchdBlockParams(Seq( 337 IssueBlockParams(Seq( 338 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 339 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 340 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 341 IssueBlockParams(Seq( 342 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 343 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 344 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 345 IssueBlockParams(Seq( 346 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 347 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 348 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 349 IssueBlockParams(Seq( 350 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 351 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 352 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 353 ), 354 numPregs = intPreg.numEntries, 355 numDeqOutside = 0, 356 schdType = schdType, 357 rfDataWidth = intPreg.dataCfg.dataWidth, 358 numUopIn = dpParams.IntDqDeqWidth, 359 ) 360 } 361 val vfSchdParams = { 362 implicit val schdType: SchedulerType = VfScheduler() 363 SchdBlockParams(Seq( 364 IssueBlockParams(Seq( 365 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VimacCfg), Seq(VfWB(port = 5, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 366 ExeUnitParams("VFEX1", Seq(VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, VSetRvfWvfCfg), Seq(VfWB(port = 6, 1), IntWB(port = 1, 2)), Seq(Seq(VfRD(5, 1)), Seq(VfRD(6, 1)), Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)))), 367 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 368 IssueBlockParams(Seq( 369 ExeUnitParams("VFEX2", Seq(VfaluCfg, VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 370 ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(VfRD(3, 1)), Seq(VfRD(4, 1)))), 371 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 372 ), 373 numPregs = vfPreg.numEntries, 374 numDeqOutside = 0, 375 schdType = schdType, 376 rfDataWidth = vfPreg.dataCfg.dataWidth, 377 numUopIn = dpParams.FpDqDeqWidth, 378 ) 379 } 380 381 val memSchdParams = { 382 implicit val schdType: SchedulerType = MemScheduler() 383 val rfDataWidth = 64 384 385 SchdBlockParams(Seq( 386 IssueBlockParams(Seq( 387 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 388 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 389 IssueBlockParams(Seq( 390 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 391 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 392 IssueBlockParams(Seq( 393 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 394 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 395 IssueBlockParams(Seq( 396 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 397 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 398 IssueBlockParams(Seq( 399 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 400 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 401 IssueBlockParams(Seq( 402 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 403 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 404 IssueBlockParams(Seq( 405 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))), 406 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 407 IssueBlockParams(Seq( 408 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 ), 411 numPregs = intPreg.numEntries max vfPreg.numEntries, 412 numDeqOutside = 0, 413 schdType = schdType, 414 rfDataWidth = rfDataWidth, 415 numUopIn = dpParams.LsDqDeqWidth, 416 ) 417 } 418 419 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 420 421 def iqWakeUpParams = { 422 Seq( 423 WakeUpConfig( 424 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 425 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 426 ), 427 ).flatten 428 } 429 430 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 431 432 val backendParams: BackendParams = backend.BackendParams( 433 Map( 434 IntScheduler() -> intSchdParams, 435 VfScheduler() -> vfSchdParams, 436 MemScheduler() -> memSchdParams, 437 ), 438 Seq( 439 intPreg, 440 vfPreg, 441 fakeIntPreg 442 ), 443 iqWakeUpParams, 444 ) 445} 446 447case object DebugOptionsKey extends Field[DebugOptions] 448 449case class DebugOptions 450( 451 FPGAPlatform: Boolean = false, 452 EnableDifftest: Boolean = false, 453 AlwaysBasicDiff: Boolean = true, 454 EnableDebug: Boolean = false, 455 EnablePerfDebug: Boolean = true, 456 UseDRAMSim: Boolean = false, 457 EnableConstantin: Boolean = false, 458 EnableChiselDB: Boolean = false, 459 AlwaysBasicDB: Boolean = true, 460 EnableTopDown: Boolean = false, 461 EnableRollingDB: Boolean = false 462) 463 464trait HasXSParameter { 465 466 implicit val p: Parameters 467 468 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 469 470 val coreParams = p(XSCoreParamsKey) 471 val env = p(DebugOptionsKey) 472 473 val XLEN = coreParams.XLEN 474 val VLEN = coreParams.VLEN 475 val ELEN = coreParams.ELEN 476 val minFLen = 32 477 val fLen = 64 478 def xLen = XLEN 479 480 val HasMExtension = coreParams.HasMExtension 481 val HasCExtension = coreParams.HasCExtension 482 val HasDiv = coreParams.HasDiv 483 val HasIcache = coreParams.HasICache 484 val HasDcache = coreParams.HasDCache 485 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 486 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 487 val AsidLength = coreParams.AsidLength 488 val ReSelectLen = coreParams.ReSelectLen 489 val AddrBytes = AddrBits / 8 // unused 490 val DataBits = XLEN 491 val DataBytes = DataBits / 8 492 val VDataBytes = VLEN / 8 493 val HasFPU = coreParams.HasFPU 494 val HasVPU = coreParams.HasVPU 495 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 496 val FetchWidth = coreParams.FetchWidth 497 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 498 val EnableBPU = coreParams.EnableBPU 499 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 500 val EnableRAS = coreParams.EnableRAS 501 val EnableLB = coreParams.EnableLB 502 val EnableLoop = coreParams.EnableLoop 503 val EnableSC = coreParams.EnableSC 504 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 505 val HistoryLength = coreParams.HistoryLength 506 val EnableGHistDiff = coreParams.EnableGHistDiff 507 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 508 val EnableClockGate = coreParams.EnableClockGate 509 val UbtbGHRLength = coreParams.UbtbGHRLength 510 val UbtbSize = coreParams.UbtbSize 511 val EnableFauFTB = coreParams.EnableFauFTB 512 val FtbSize = coreParams.FtbSize 513 val FtbWays = coreParams.FtbWays 514 val RasSize = coreParams.RasSize 515 val RasSpecSize = coreParams.RasSpecSize 516 val RasCtrSize = coreParams.RasCtrSize 517 518 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 519 coreParams.branchPredictor(resp_in, p) 520 } 521 val numBr = coreParams.numBr 522 val TageTableInfos = coreParams.TageTableInfos 523 val TageBanks = coreParams.numBr 524 val SCNRows = coreParams.SCNRows 525 val SCCtrBits = coreParams.SCCtrBits 526 val SCHistLens = coreParams.SCHistLens 527 val SCNTables = coreParams.SCNTables 528 529 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 530 case ((n, cb), h) => (n, cb, h) 531 } 532 val ITTageTableInfos = coreParams.ITTageTableInfos 533 type FoldedHistoryInfo = Tuple2[Int, Int] 534 val foldedGHistInfos = 535 (TageTableInfos.map{ case (nRows, h, t) => 536 if (h > 0) 537 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 538 else 539 Set[FoldedHistoryInfo]() 540 }.reduce(_++_).toSet ++ 541 SCTableInfos.map{ case (nRows, _, h) => 542 if (h > 0) 543 Set((h, min(log2Ceil(nRows/TageBanks), h))) 544 else 545 Set[FoldedHistoryInfo]() 546 }.reduce(_++_).toSet ++ 547 ITTageTableInfos.map{ case (nRows, h, t) => 548 if (h > 0) 549 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 550 else 551 Set[FoldedHistoryInfo]() 552 }.reduce(_++_) ++ 553 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 554 ).toList 555 556 557 558 val CacheLineSize = coreParams.CacheLineSize 559 val CacheLineHalfWord = CacheLineSize / 16 560 val ExtHistoryLength = HistoryLength + 64 561 val ICacheECCForceError = coreParams.ICacheECCForceError 562 val IBufSize = coreParams.IBufSize 563 val IBufNBank = coreParams.IBufNBank 564 val backendParams: BackendParams = coreParams.backendParams 565 val DecodeWidth = coreParams.DecodeWidth 566 val RenameWidth = coreParams.RenameWidth 567 val CommitWidth = coreParams.CommitWidth 568 val MaxUopSize = coreParams.MaxUopSize 569 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 570 val RenameSnapshotNum = coreParams.RenameSnapshotNum 571 val FtqSize = coreParams.FtqSize 572 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 573 val IntLogicRegs = coreParams.IntLogicRegs 574 val FpLogicRegs = coreParams.FpLogicRegs 575 val VecLogicRegs = coreParams.VecLogicRegs 576 val VCONFIG_IDX = coreParams.VCONFIG_IDX 577 val IntPhyRegs = coreParams.intPreg.numEntries 578 val VfPhyRegs = coreParams.vfPreg.numEntries 579 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 580 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 581 val RobSize = coreParams.RobSize 582 val RabSize = coreParams.RabSize 583 val VTypeBufferSize = coreParams.VTypeBufferSize 584 /** 585 * the minimum element length of vector elements 586 */ 587 val minVecElen: Int = coreParams.minVecElen 588 589 /** 590 * the maximum number of elements in vector register 591 */ 592 val maxElemPerVreg: Int = coreParams.maxElemPerVreg 593 594 val IntRefCounterWidth = log2Ceil(RobSize) 595 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 596 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 597 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 598 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 599 val LoadQueueRARSize = coreParams.LoadQueueRARSize 600 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 601 val RollbackGroupSize = coreParams.RollbackGroupSize 602 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 603 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 604 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 605 val StoreQueueSize = coreParams.StoreQueueSize 606 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 607 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 608 val VlsQueueSize = coreParams.VlsQueueSize 609 val dpParams = coreParams.dpParams 610 611 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 612 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 613 614 val NumRedirect = backendParams.numRedirect 615 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 616 val FtqRedirectAheadNum = NumRedirect 617 val LoadPipelineWidth = coreParams.LoadPipelineWidth 618 val StorePipelineWidth = coreParams.StorePipelineWidth 619 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 620 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 621 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 622 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 623 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 624 val StoreBufferSize = coreParams.StoreBufferSize 625 val StoreBufferThreshold = coreParams.StoreBufferThreshold 626 val EnsbufferWidth = coreParams.EnsbufferWidth 627 val VlMergeBufferSize = coreParams.VlMergeBufferSize 628 val VsMergeBufferSize = coreParams.VsMergeBufferSize 629 val UopWritebackWidth = coreParams.UopWritebackWidth 630 val SplitBufferSize = coreParams.SplitBufferSize 631 val UncacheBufferSize = coreParams.UncacheBufferSize 632 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 633 val EnableFastForward = coreParams.EnableFastForward 634 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 635 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 636 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 637 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 638 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 639 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 640 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 641 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 642 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 643 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 644 val asidLen = coreParams.MMUAsidLen 645 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 646 val refillBothTlb = coreParams.refillBothTlb 647 val iwpuParam = coreParams.iwpuParameters 648 val dwpuParam = coreParams.dwpuParameters 649 val itlbParams = coreParams.itlbParameters 650 val ldtlbParams = coreParams.ldtlbParameters 651 val sttlbParams = coreParams.sttlbParameters 652 val hytlbParams = coreParams.hytlbParameters 653 val pftlbParams = coreParams.pftlbParameters 654 val btlbParams = coreParams.btlbParameters 655 val l2tlbParams = coreParams.l2tlbParameters 656 val NumPerfCounters = coreParams.NumPerfCounters 657 658 val instBytes = if (HasCExtension) 2 else 4 659 val instOffsetBits = log2Ceil(instBytes) 660 661 val icacheParameters = coreParams.icacheParameters 662 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 663 664 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 665 // for constrained LR/SC loop 666 val LRSCCycles = 64 667 // for lr storm 668 val LRSCBackOff = 8 669 670 // cache hierarchy configurations 671 val l1BusDataWidth = 256 672 673 // load violation predict 674 val ResetTimeMax2Pow = 20 //1078576 675 val ResetTimeMin2Pow = 10 //1024 676 // wait table parameters 677 val WaitTableSize = 1024 678 val MemPredPCWidth = log2Up(WaitTableSize) 679 val LWTUse2BitCounter = true 680 // store set parameters 681 val SSITSize = WaitTableSize 682 val LFSTSize = 32 683 val SSIDWidth = log2Up(LFSTSize) 684 val LFSTWidth = 4 685 val StoreSetEnable = true // LWT will be disabled if SS is enabled 686 val LFSTEnable = true 687 688 val PCntIncrStep: Int = 6 689 val numPCntHc: Int = 25 690 val numPCntPtw: Int = 19 691 692 val numCSRPCntFrontend = 8 693 val numCSRPCntCtrl = 8 694 val numCSRPCntLsu = 8 695 val numCSRPCntHc = 5 696 val printEventCoding = true 697 698 // Parameters for Sdtrig extension 699 protected val TriggerNum = 4 700 protected val TriggerChainMaxLength = 2 701} 702