xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 25df626ec34ea3250afaec2b5e8ea334ab760b4a) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19import xiangshan.backend.fu.vector.Bundles.VSew
20
21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
22  override def shouldBeInlined: Boolean = false
23
24  implicit val iqParams = params
25  lazy val module: IssueQueueImp = iqParams.schdType match {
26    case IntScheduler() => new IssueQueueIntImp(this)
27    case VfScheduler() => new IssueQueueVfImp(this)
28    case MemScheduler() =>
29      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
30      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
31      else new IssueQueueIntImp(this)
32    case _ => null
33  }
34}
35
36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
37  val empty = Output(Bool())
38  val full = Output(Bool())
39  val validCnt = Output(UInt(log2Ceil(numEntries).W))
40  val leftVec = Output(Vec(numEnq + 1, Bool()))
41}
42
43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
44
45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
46  // Inputs
47  val flush = Flipped(ValidIO(new Redirect))
48  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
49
50  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
52  val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
54  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
55  val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
56  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
57  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
58  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
59  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
60  val vlIsZero = Input(Bool())
61  val vlIsVlmax = Input(Bool())
62  val og0Cancel = Input(ExuOH(backendParams.numExu))
63  val og1Cancel = Input(ExuOH(backendParams.numExu))
64  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
65
66  // Outputs
67  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
68  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
69  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
70  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
71
72  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
73  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
74}
75
76class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
77  extends LazyModuleImp(wrapper)
78  with HasXSParameter {
79
80  override def desiredName: String = s"${params.getIQName}"
81
82  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
83    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
84    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
85    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
86    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
87    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
88
89  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
90  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
91  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
92  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
93
94  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
95  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
96  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
97  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
98  val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap)
99
100  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}")
101  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
102  lazy val io = IO(new IssueQueueIO())
103
104  // Modules
105  val entries = Module(new Entries)
106  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
107  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
108  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
109  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
110  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
111  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
112
113  class WakeupQueueFlush extends Bundle {
114    val redirect = ValidIO(new Redirect)
115    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
116    val og0Fail = Output(Bool())
117    val og1Fail = Output(Bool())
118  }
119
120  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
121    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
122    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
123    val ogFailFlush = stage match {
124      case 1 => flush.og0Fail
125      case 2 => flush.og1Fail
126      case _ => false.B
127    }
128    redirectFlush || loadDependencyFlush || ogFailFlush
129  }
130
131  private def modificationFunc(exuInput: ExuInput): ExuInput = {
132    val newExuInput = WireDefault(exuInput)
133    newExuInput.loadDependency match {
134      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
135      case None =>
136    }
137    newExuInput
138  }
139
140  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
141    val lastExuInput = WireDefault(exuInput)
142    val newExuInput = WireDefault(newInput)
143    newExuInput.elements.foreach { case (name, data) =>
144      if (lastExuInput.elements.contains(name)) {
145        data := lastExuInput.elements(name)
146      }
147    }
148    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
149      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
150    }
151    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
152      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
153    }
154    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
155      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
156    }
157    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
158      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
159    }
160    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
161      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
162    }
163    newExuInput
164  }
165
166  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
167    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
168  ))}
169  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
170
171  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
172  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
173  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
174  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
175  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
176  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
177  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
178  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
179  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
180  val s0_enqValidVec = io.enq.map(_.valid)
181  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
182  val s0_enqNotFlush = !io.flush.valid
183  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
184  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
185
186
187  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
188  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
189
190  val validVec = VecInit(entries.io.valid.asBools)
191  val canIssueVec = VecInit(entries.io.canIssue.asBools)
192  dontTouch(canIssueVec)
193  val deqFirstIssueVec = entries.io.isFirstIssue
194
195  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
196  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
197  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
198  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
199  // (entryIdx)(srcIdx)(exuIdx)
200  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
201  // (deqIdx)(srcIdx)(exuIdx)
202  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
203
204  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
205  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
206  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
207  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
208
209  //deq
210  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
211  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
212  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
213  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
214  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
215  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
216  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
217
218  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
219  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
220  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
221
222  //trans
223  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
224  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
225  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
226  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
227  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
228
229  // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle
230  // as vf exu's min latency is 1, we do not need consider og0cancel
231  val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ))
232  wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) =>
233    if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) {
234      val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel)
235      w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w)))
236      w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) }
237    } else {
238      w := w_src
239    }
240  }
241
242  /**
243    * Connection of [[entries]]
244    */
245  entries.io match { case entriesIO: EntriesIO =>
246    entriesIO.flush                                             := io.flush
247    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
248      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
249      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
250      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
251      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
252      for(j <- 0 until numLsrc) {
253        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
254        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
255        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
256        enq.bits.status.srcStatus(j).dataSources.value          := Mux(
257          SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
258          DataSource.zero,
259          Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg)
260        )
261        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1))
262        if(params.hasIQWakeUp) {
263          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
264        }
265      }
266      enq.bits.status.blocked                                   := false.B
267      enq.bits.status.issued                                    := false.B
268      enq.bits.status.firstIssue                                := false.B
269      enq.bits.status.issueTimer                                := "b11".U
270      enq.bits.status.deqPortIdx                                := 0.U
271      enq.bits.imm.foreach(_                                    := s0_enqBits(enqIdx).imm)
272      enq.bits.payload                                          := s0_enqBits(enqIdx)
273    }
274    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
275      og0Resp                                                   := io.og0Resp(i)
276    }
277    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
278      og1Resp                                                   := io.og1Resp(i)
279    }
280    if (params.inVfSchd) {
281      entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) =>
282        og2Resp                                                 := io.og2Resp.get(i)
283      }
284    }
285    if (params.isLdAddrIQ || params.isHyAddrIQ) {
286      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
287        finalIssueResp                                          := io.finalIssueResp.get(i)
288      }
289      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
290        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
291      }
292    }
293    if (params.isVecLduIQ) {
294      entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) =>
295        resp                                                    := io.vecLoadIssueResp.get(i)
296      }
297    }
298    for(deqIdx <- 0 until params.numDeq) {
299      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
300      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
301      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
302      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
303      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
304      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
305      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
306      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
307      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
308    }
309    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
310    entriesIO.wakeUpFromIQ                                      := wakeupFromIQ
311    entriesIO.vlIsZero                                          := io.vlIsZero
312    entriesIO.vlIsVlmax                                         := io.vlIsVlmax
313    entriesIO.og0Cancel                                         := io.og0Cancel
314    entriesIO.og1Cancel                                         := io.og1Cancel
315    entriesIO.ldCancel                                          := io.ldCancel
316    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
317    //output
318    fuTypeVec                                                   := entriesIO.fuType
319    deqEntryVec                                                 := entriesIO.deqEntry
320    cancelDeqVec                                                := entriesIO.cancelDeqVec
321    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
322    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
323    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
324  }
325
326
327  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
328
329  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
330    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
331  ).reverse)
332
333  // if deq port can accept the uop
334  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
335    Cat(fuTypeVec.map(fuType =>
336      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
337    ).reverse)
338  }
339
340  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
341    fuTypeVec.map(fuType =>
342      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
343  }
344
345  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
346    val mergeFuBusy = {
347      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
348      else canIssueVec.asUInt
349    }
350    val mergeIntWbBusy = {
351      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
352      else mergeFuBusy
353    }
354    val mergeVfWbBusy = {
355      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
356      else mergeIntWbBusy
357    }
358    merge := mergeVfWbBusy
359  }
360
361  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
362    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
363  }
364  dontTouch(fuTypeVec)
365  dontTouch(canIssueMergeAllBusy)
366  dontTouch(deqCanIssue)
367
368  if (params.numDeq == 2) {
369    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
370  }
371
372  if (params.numDeq == 2 && params.deqFuSame) {
373    val subDeqPolicy = Module(new DeqPolicy())
374
375    enqEntryOldestSel := DontCare
376
377    if (params.isAllComp || params.isAllSimp) {
378      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
379        enq = othersEntryEnqSelVec.get,
380        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
381      )
382      othersEntryOldestSel(1) := DontCare
383
384      subDeqPolicy.io.request := subDeqRequest.get
385      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
386      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
387    }
388    else {
389      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
390      simpAgeDetectRequest.get(1) := DontCare
391      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
392      if (params.numEnq == 2) {
393        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
394      }
395
396      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
397        enq = simpEntryEnqSelVec.get,
398        canIssue = simpAgeDetectRequest.get
399      )
400
401      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
402        enq = compEntryEnqSelVec.get,
403        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
404      )
405      compEntryOldestSel.get(1) := DontCare
406
407      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
408      othersEntryOldestSel(0).bits := Cat(
409        compEntryOldestSel.get(0).bits,
410        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
411      )
412      othersEntryOldestSel(1) := DontCare
413
414      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
415      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
416      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
417    }
418
419    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
420
421    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
422    deqSelValidVec(1) := subDeqSelValidVec.get(0)
423    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
424                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
425                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
426    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
427
428    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
429      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
430      selOH := deqOH
431    }
432  }
433  else {
434    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
435      enq = VecInit(s0_doEnqSelValidVec),
436      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
437    )
438
439    if (params.isAllComp || params.isAllSimp) {
440      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
441        enq = othersEntryEnqSelVec.get,
442        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
443      )
444
445      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
446        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
447          selValid := false.B
448          selOH := 0.U.asTypeOf(selOH)
449        } else {
450          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
451          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
452        }
453      }
454    }
455    else {
456      othersEntryOldestSel := DontCare
457
458      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
459        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
460      }
461      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
462      if (params.numEnq == 2) {
463        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
464      }
465
466      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
467        enq = simpEntryEnqSelVec.get,
468        canIssue = simpAgeDetectRequest.get
469      )
470
471      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
472        enq = compEntryEnqSelVec.get,
473        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
474      )
475
476      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
477        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
478          selValid := false.B
479          selOH := 0.U.asTypeOf(selOH)
480        } else {
481          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
482          selOH := Cat(
483            compEntryOldestSel.get(i).bits,
484            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
485            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
486          )
487        }
488      }
489    }
490
491    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
492      selValid := deqValid && deqBeforeDly(i).ready
493      selOH := deqOH
494    }
495  }
496
497  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
498
499  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
500    deqResp.valid := finalDeqSelValidVec(i)
501    deqResp.bits.resp   := RespType.success
502    deqResp.bits.robIdx := DontCare
503    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
504    deqResp.bits.uopIdx.foreach(_ := DontCare)
505  }
506
507  //fuBusyTable
508  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
509    if(busyTableWrite.nonEmpty) {
510      val btwr = busyTableWrite.get
511      val btrd = busyTableRead.get
512      btwr.io.in.deqResp := toBusyTableDeqResp(i)
513      btwr.io.in.og0Resp := io.og0Resp(i)
514      btwr.io.in.og1Resp := io.og1Resp(i)
515      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
516      btrd.io.in.fuTypeRegVec := fuTypeVec
517      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
518    }
519    else {
520      fuBusyTableMask(i) := 0.U(params.numEntries.W)
521    }
522  }
523
524  //wbfuBusyTable write
525  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
526    if(busyTableWrite.nonEmpty) {
527      val btwr = busyTableWrite.get
528      val bt = busyTable.get
529      val dq = deqResp.get
530      btwr.io.in.deqResp := toBusyTableDeqResp(i)
531      btwr.io.in.og0Resp := io.og0Resp(i)
532      btwr.io.in.og1Resp := io.og1Resp(i)
533      bt := btwr.io.out.fuBusyTable
534      dq := btwr.io.out.deqRespSet
535    }
536  }
537
538  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
539    if (busyTableWrite.nonEmpty) {
540      val btwr = busyTableWrite.get
541      val bt = busyTable.get
542      val dq = deqResp.get
543      btwr.io.in.deqResp := toBusyTableDeqResp(i)
544      btwr.io.in.og0Resp := io.og0Resp(i)
545      btwr.io.in.og1Resp := io.og1Resp(i)
546      bt := btwr.io.out.fuBusyTable
547      dq := btwr.io.out.deqRespSet
548    }
549  }
550
551  //wbfuBusyTable read
552  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
553    if(busyTableRead.nonEmpty) {
554      val btrd = busyTableRead.get
555      val bt = busyTable.get
556      btrd.io.in.fuBusyTable := bt
557      btrd.io.in.fuTypeRegVec := fuTypeVec
558      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
559    }
560    else {
561      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
562    }
563  }
564  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
565    if (busyTableRead.nonEmpty) {
566      val btrd = busyTableRead.get
567      val bt = busyTable.get
568      btrd.io.in.fuBusyTable := bt
569      btrd.io.in.fuTypeRegVec := fuTypeVec
570      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
571    }
572    else {
573      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
574    }
575  }
576
577  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
578    wakeUpQueueOption.foreach {
579      wakeUpQueue =>
580        val flush = Wire(new WakeupQueueFlush)
581        flush.redirect := io.flush
582        flush.ldCancel := io.ldCancel
583        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
584        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
585        wakeUpQueue.io.flush := flush
586        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
587        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
588        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
589        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
590    }
591  }
592
593  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
594    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
595    deq.bits.addrOH          := finalDeqSelOHVec(i)
596    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
597    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
598    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
599    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
600    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
601    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
602    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
603    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
604    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
605    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
606
607    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
608    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
609    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
610    deq.bits.common.srcTimer.foreach(_ := DontCare)
611    deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i))
612    deq.bits.common.src := DontCare
613    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
614
615    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
616      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
617      rf.foreach(_.addr := psrc)
618      rf.foreach(_.srcType := srcType)
619    }
620    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
621      sink := source
622    }
623    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
624    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
625
626    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
627    deq.bits.common.perfDebugInfo.selectTime := GTimer()
628    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
629  }
630
631  io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) =>
632    NewPipelineConnect(
633      deq, deqDly, deqDly.valid,
634      false.B,
635      Option("Scheduler2DataPathPipe")
636    )
637  }
638  if(backendParams.debugEn) {
639    dontTouch(io.deqDelay)
640  }
641  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
642    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
643      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
644      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
645      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
646      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
647    } else if (wakeUpQueues(i).nonEmpty) {
648      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
649      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
650      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
651      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
652    } else {
653      wakeup.valid := false.B
654      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
655      wakeup.bits.is0Lat :=  0.U
656    }
657    if (wakeUpQueues(i).nonEmpty) {
658      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
659      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
660      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
661    }
662
663    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
664      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
665    }
666    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
667      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
668    }
669    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
670      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
671    }
672    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
673      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
674    }
675    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
676      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
677    }
678  }
679
680  // Todo: better counter implementation
681  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
682  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
683  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
684  private val enqEntryValidCntDeq0 = PopCount(
685    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
686  )
687  private val othersValidCntDeq0 = PopCount(
688    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
689  )
690  private val enqEntryValidCntDeq1 = PopCount(
691    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
692  )
693  private val othersValidCntDeq1 = PopCount(
694    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
695  )
696  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
697    io.enq.map(_.bits.fuType).map(fuType =>
698      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
699  }
700  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
701  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
702  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
703  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
704  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
705  for (i <- 0 until params.numEnq) {
706    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
707  }
708  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
709  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
710    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
711  }
712  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
713  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
714
715  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
716  io.status.empty := !Cat(validVec).orR
717  io.status.full := othersCanotIn
718  io.status.validCnt := PopCount(validVec)
719
720  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
721    Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
722  }
723
724  // issue perf counter
725  // enq count
726  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
727  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
728  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
729  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
730  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
731  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
732  // valid count
733  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
734  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
735  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
736  // only split when more than 1 func type
737  if (params.getFuCfgs.size > 0) {
738    for (t <- FuType.functionNameMap.keys) {
739      val fuName = FuType.functionNameMap(t)
740      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
741        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
742      }
743    }
744  }
745  // ready instr count
746  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
747  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
748  // only split when more than 1 func type
749  if (params.getFuCfgs.size > 0) {
750    for (t <- FuType.functionNameMap.keys) {
751      val fuName = FuType.functionNameMap(t)
752      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
753        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
754      }
755    }
756  }
757
758  // deq instr count
759  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
760  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
761  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
762  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
763
764  // deq instr data source count
765  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
766    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
767  }.reduce(_ +& _))
768  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
769    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
770  }.reduce(_ +& _))
771  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
772    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
773  }.reduce(_ +& _))
774  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
775    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
776  }.reduce(_ +& _))
777
778  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
779    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
780  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
781  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
782    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
783  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
784  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
785    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
786  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
787  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
788    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
789  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
790
791  // deq instr data source count for each futype
792  for (t <- FuType.functionNameMap.keys) {
793    val fuName = FuType.functionNameMap(t)
794    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
795      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
796        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
797      }.reduce(_ +& _))
798      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
799        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
800      }.reduce(_ +& _))
801      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
802        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
803      }.reduce(_ +& _))
804      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
805        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
806      }.reduce(_ +& _))
807
808      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
809        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
810      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
811      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
812        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
813      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
814      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
815        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
816      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
817      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
818        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
819      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
820    }
821  }
822}
823
824class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
825  val fastMatch = UInt(backendParams.LduCnt.W)
826  val fastImm = UInt(12.W)
827}
828
829class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
830
831class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
832  extends IssueQueueImp(wrapper)
833{
834  io.suggestName("none")
835  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
836
837  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
838    deq.bits.common.pc.foreach(_ := DontCare)
839    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
840    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
841    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
842    deq.bits.common.predictInfo.foreach(x => {
843      x.target := DontCare
844      x.taken := deqEntryVec(i).bits.payload.pred_taken
845    })
846    // for std
847    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
848    // for i2f
849    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
850  }}
851}
852
853class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
854  extends IssueQueueImp(wrapper)
855{
856  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
857    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
858    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
859    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
860    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
861  }}
862}
863
864class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
865  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ)))
866
867  // TODO: is still needed?
868  val checkWait = new Bundle {
869    val stIssuePtr = Input(new SqPtr)
870    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
871  }
872  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
873
874  // load wakeup
875  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
876
877  // vector
878  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
879  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
880}
881
882class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
883  val memIO = Some(new IssueQueueMemBundle)
884}
885
886class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
887  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
888
889  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
890    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
891  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
892
893  io.suggestName("none")
894  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
895  private val memIO = io.memIO.get
896
897  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
898
899  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
900    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
901    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
902    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
903    slowResp.bits.fuType := DontCare
904  }
905
906  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
907    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
908    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
909    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
910    fastResp.bits.fuType := DontCare
911  }
912
913  // load wakeup
914  val loadWakeUpIter = memIO.loadWakeUp.iterator
915  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
916    if (param.hasLoadExu) {
917      require(wakeUpQueues(i).isEmpty)
918      val uop = loadWakeUpIter.next()
919
920      wakeup.valid := GatedValidRegNext(uop.fire)
921      wakeup.bits.rfWen  := GatedValidRegNext(uop.bits.rfWen  && uop.fire)
922      wakeup.bits.fpWen  := GatedValidRegNext(uop.bits.fpWen  && uop.fire)
923      wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire)
924      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
925      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
926
927      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen  && uop.fire)))
928      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen  && uop.fire)))
929      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire)))
930      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
931      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
932
933      wakeup.bits.is0Lat := 0.U
934    }
935  }
936  require(!loadWakeUpIter.hasNext)
937
938  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
939    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
940    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
941    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
942    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
943    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
944    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
945    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
946    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
947    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
948  }
949}
950
951class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
952  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
953
954  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
955  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
956
957  io.suggestName("none")
958  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
959  private val memIO = io.memIO.get
960
961  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
962
963  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
964    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
965    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
966      (if (j < i) !valid(j) || compareVec(i)(j)
967      else if (j == i) valid(i)
968      else !valid(j) || !compareVec(j)(i))
969    )).andR))
970    resultOnehot
971  }
972
973  val robIdxVec = entries.io.robIdx.get
974  val uopIdxVec = entries.io.uopIdx.get
975  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
976
977  deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
978  deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
979  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready
980  finalDeqSelOHVec.head := deqSelOHVec.head
981
982  for (i <- entries.io.enq.indices) {
983    entries.io.enq(i).bits.status match { case enqData =>
984      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
985      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
986      // MemAddrIQ also handle vector insts
987      enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem
988      enqData.blocked          := false.B
989    }
990  }
991
992  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
993    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
994    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
995    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
996    slowResp.bits.fuType           := DontCare
997    slowResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get
998  }
999
1000  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1001    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1002    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1003    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1004    fastResp.bits.fuType           := DontCare
1005    fastResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get
1006  }
1007
1008  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1009  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1010
1011  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1012    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1013    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1014    deq.bits.common.numLsElem.get := deqEntryVec(i).bits.status.vecMem.get.numLsElem
1015    deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem)
1016    if (params.isVecLduIQ) {
1017      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1018      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1019    }
1020    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1021    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1022    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1023    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1024  }
1025
1026  io.vecLoadIssueResp.foreach(dontTouch(_))
1027}
1028