xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 17985fbbb1c69e82059f583150a6eff05516032d) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19
20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
21  override def shouldBeInlined: Boolean = false
22
23  implicit val iqParams = params
24  lazy val module: IssueQueueImp = iqParams.schdType match {
25    case IntScheduler() => new IssueQueueIntImp(this)
26    case VfScheduler() => new IssueQueueVfImp(this)
27    case MemScheduler() =>
28      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
29      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
30      else new IssueQueueIntImp(this)
31    case _ => null
32  }
33}
34
35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
36  val empty = Output(Bool())
37  val full = Output(Bool())
38  val validCnt = Output(UInt(log2Ceil(numEntries).W))
39  val leftVec = Output(Vec(numEnq + 1, Bool()))
40}
41
42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
43
44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
45  // Inputs
46  val flush = Flipped(ValidIO(new Redirect))
47  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
48
49  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
54  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
55  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
56  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
57  val og0Cancel = Input(ExuOH(backendParams.numExu))
58  val og1Cancel = Input(ExuOH(backendParams.numExu))
59  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
65  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
66
67  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
68  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
69}
70
71class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
72  extends LazyModuleImp(wrapper)
73  with HasXSParameter {
74
75  override def desiredName: String = s"${params.getIQName}"
76
77  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
78    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
79    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
80    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
81    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
82    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
83
84  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
85  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
86  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
87  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
88
89  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
90  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
91  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
92  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
93  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
94
95  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
96  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
97  lazy val io = IO(new IssueQueueIO())
98
99  // Modules
100  val entries = Module(new Entries)
101  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
102  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
103  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
104  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
105  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
106  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
107
108  class WakeupQueueFlush extends Bundle {
109    val redirect = ValidIO(new Redirect)
110    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
111    val og0Fail = Output(Bool())
112    val og1Fail = Output(Bool())
113  }
114
115  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
116    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
117    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
118    val ogFailFlush = stage match {
119      case 1 => flush.og0Fail
120      case 2 => flush.og1Fail
121      case _ => false.B
122    }
123    redirectFlush || loadDependencyFlush || ogFailFlush
124  }
125
126  private def modificationFunc(exuInput: ExuInput): ExuInput = {
127    val newExuInput = WireDefault(exuInput)
128    newExuInput.loadDependency match {
129      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
130      case None =>
131    }
132    newExuInput
133  }
134
135  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
136    val lastExuInput = WireDefault(exuInput)
137    val newExuInput = WireDefault(newInput)
138    newExuInput.elements.foreach { case (name, data) =>
139      if (lastExuInput.elements.contains(name)) {
140        data := lastExuInput.elements(name)
141      }
142    }
143    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
144      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
145    }
146    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
147      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
148    }
149    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
150      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
151    }
152    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
153      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
154    }
155    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
156      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
157    }
158    newExuInput
159  }
160
161  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
162    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
163  ))}
164  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
165
166  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
167  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
168  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
169  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
170  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
171  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
172  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
173  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
174  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
175  val s0_enqValidVec = io.enq.map(_.valid)
176  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
177  val s0_enqNotFlush = !io.flush.valid
178  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
179  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
180
181
182  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
183  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
184
185  val validVec = VecInit(entries.io.valid.asBools)
186  val canIssueVec = VecInit(entries.io.canIssue.asBools)
187  dontTouch(canIssueVec)
188  val deqFirstIssueVec = entries.io.isFirstIssue
189
190  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
191  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
192  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
193  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
194  // (entryIdx)(srcIdx)(exuIdx)
195  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
196  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
197
198  // (deqIdx)(srcIdx)(exuIdx)
199  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
200  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
201
202  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
203  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
204  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
205  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
206
207  //deq
208  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
209  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
210  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
211  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
212  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
213  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
214  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
215
216  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
217  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
218  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
219
220  //trans
221  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
222  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
223  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
224  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
225  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
226
227  /**
228    * Connection of [[entries]]
229    */
230  entries.io match { case entriesIO: EntriesIO =>
231    entriesIO.flush                                             := io.flush
232    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
233      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
234      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
235      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
236      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
237      for(j <- 0 until numLsrc) {
238        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
239        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
240        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
241        enq.bits.status.srcStatus(j).dataSources.value          := Mux(
242          SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
243          DataSource.zero,
244          Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg)
245        )
246        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1))
247        if(params.hasIQWakeUp) {
248          enq.bits.status.srcStatus(j).srcTimer.get             := 0.U(3.W)
249          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
250        }
251      }
252      enq.bits.status.blocked                                   := false.B
253      enq.bits.status.issued                                    := false.B
254      enq.bits.status.firstIssue                                := false.B
255      enq.bits.status.issueTimer                                := "b10".U
256      enq.bits.status.deqPortIdx                                := 0.U
257      if (params.inIntSchd && params.AluCnt > 0) {
258        // dirty code for lui+addi(w) fusion
259        val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32
260        val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0))
261        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm))
262      }
263      else if (params.inMemSchd && params.LduCnt > 0) {
264        // dirty code for fused_lui_load
265        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType)
266        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm))
267      }
268      else {
269        enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm)
270      }
271      enq.bits.payload                                          := s0_enqBits(enqIdx)
272    }
273    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
274      og0Resp                                                   := io.og0Resp(i)
275    }
276    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
277      og1Resp                                                   := io.og1Resp(i)
278    }
279    entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) =>
280      finalIssueResp                                            := io.finalIssueResp.get(i)
281    })
282    entriesIO.memAddrIssueResp.foreach(_. zipWithIndex.foreach { case (memAddrIssueResp, i) =>
283      memAddrIssueResp                                          := io.memAddrIssueResp.get(i)
284    })
285    for(deqIdx <- 0 until params.numDeq) {
286      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
287      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
288      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
289      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
290      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
291      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
292      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
293      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
294      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
295    }
296    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
297    entriesIO.wakeUpFromIQ                                      := io.wakeupFromIQ
298    entriesIO.og0Cancel                                         := io.og0Cancel
299    entriesIO.og1Cancel                                         := io.og1Cancel
300    entriesIO.ldCancel                                          := io.ldCancel
301    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
302    //output
303    fuTypeVec                                                   := entriesIO.fuType
304    deqEntryVec                                                 := entriesIO.deqEntry
305    cancelDeqVec                                                := entriesIO.cancelDeqVec
306    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
307    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
308    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
309  }
310
311
312  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
313
314  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
315    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
316  ).reverse)
317
318  // if deq port can accept the uop
319  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
320    Cat(fuTypeVec.map(fuType =>
321      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
322    ).reverse)
323  }
324
325  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
326    fuTypeVec.map(fuType =>
327      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
328  }
329
330  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
331    val mergeFuBusy = {
332      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
333      else canIssueVec.asUInt
334    }
335    val mergeIntWbBusy = {
336      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
337      else mergeFuBusy
338    }
339    val mergeVfWbBusy = {
340      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
341      else mergeIntWbBusy
342    }
343    merge := mergeVfWbBusy
344  }
345
346  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
347    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
348  }
349  dontTouch(fuTypeVec)
350  dontTouch(canIssueMergeAllBusy)
351  dontTouch(deqCanIssue)
352
353  if (params.numDeq == 2) {
354    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
355  }
356
357  if (params.numDeq == 2 && params.deqFuSame) {
358    val subDeqPolicy = Module(new DeqPolicy())
359
360    enqEntryOldestSel := DontCare
361
362    if (params.isAllComp || params.isAllSimp) {
363      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
364        enq = othersEntryEnqSelVec.get,
365        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
366      )
367      othersEntryOldestSel(1) := DontCare
368
369      subDeqPolicy.io.request := subDeqRequest.get
370      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
371      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
372    }
373    else {
374      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
375      simpAgeDetectRequest.get(1) := DontCare
376      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
377      if (params.numEnq == 2) {
378        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
379      }
380
381      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
382        enq = simpEntryEnqSelVec.get,
383        canIssue = simpAgeDetectRequest.get
384      )
385
386      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
387        enq = compEntryEnqSelVec.get,
388        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
389      )
390      compEntryOldestSel.get(1) := DontCare
391
392      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
393      othersEntryOldestSel(0).bits := Cat(
394        compEntryOldestSel.get(0).bits,
395        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
396      )
397      othersEntryOldestSel(1) := DontCare
398
399      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
400      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
401      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
402    }
403
404    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
405
406    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
407    deqSelValidVec(1) := subDeqSelValidVec.get(0)
408    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
409                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
410                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
411    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
412
413    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
414      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
415      selOH := deqOH
416    }
417  }
418  else {
419    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
420      enq = VecInit(s0_doEnqSelValidVec),
421      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
422    )
423
424    if (params.isAllComp || params.isAllSimp) {
425      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
426        enq = othersEntryEnqSelVec.get,
427        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
428      )
429
430      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
431        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
432          selValid := false.B
433          selOH := 0.U.asTypeOf(selOH)
434        } else {
435          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
436          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
437        }
438      }
439    }
440    else {
441      othersEntryOldestSel := DontCare
442
443      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
444        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
445      }
446      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
447      if (params.numEnq == 2) {
448        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
449      }
450
451      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
452        enq = simpEntryEnqSelVec.get,
453        canIssue = simpAgeDetectRequest.get
454      )
455
456      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
457        enq = compEntryEnqSelVec.get,
458        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
459      )
460
461      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
462        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
463          selValid := false.B
464          selOH := 0.U.asTypeOf(selOH)
465        } else {
466          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
467          selOH := Cat(
468            compEntryOldestSel.get(i).bits,
469            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
470            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
471          )
472        }
473      }
474    }
475
476    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
477      selValid := deqValid && deqBeforeDly(i).ready
478      selOH := deqOH
479    }
480  }
481
482  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
483
484  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
485    deqResp.valid := finalDeqSelValidVec(i)
486    deqResp.bits.resp   := RespType.success
487    deqResp.bits.robIdx := DontCare
488    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
489    deqResp.bits.uopIdx.foreach(_ := DontCare)
490  }
491
492  //fuBusyTable
493  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
494    if(busyTableWrite.nonEmpty) {
495      val btwr = busyTableWrite.get
496      val btrd = busyTableRead.get
497      btwr.io.in.deqResp := toBusyTableDeqResp(i)
498      btwr.io.in.og0Resp := io.og0Resp(i)
499      btwr.io.in.og1Resp := io.og1Resp(i)
500      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
501      btrd.io.in.fuTypeRegVec := fuTypeVec
502      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
503    }
504    else {
505      fuBusyTableMask(i) := 0.U(params.numEntries.W)
506    }
507  }
508
509  //wbfuBusyTable write
510  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
511    if(busyTableWrite.nonEmpty) {
512      val btwr = busyTableWrite.get
513      val bt = busyTable.get
514      val dq = deqResp.get
515      btwr.io.in.deqResp := toBusyTableDeqResp(i)
516      btwr.io.in.og0Resp := io.og0Resp(i)
517      btwr.io.in.og1Resp := io.og1Resp(i)
518      bt := btwr.io.out.fuBusyTable
519      dq := btwr.io.out.deqRespSet
520    }
521  }
522
523  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
524    if (busyTableWrite.nonEmpty) {
525      val btwr = busyTableWrite.get
526      val bt = busyTable.get
527      val dq = deqResp.get
528      btwr.io.in.deqResp := toBusyTableDeqResp(i)
529      btwr.io.in.og0Resp := io.og0Resp(i)
530      btwr.io.in.og1Resp := io.og1Resp(i)
531      bt := btwr.io.out.fuBusyTable
532      dq := btwr.io.out.deqRespSet
533    }
534  }
535
536  //wbfuBusyTable read
537  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
538    if(busyTableRead.nonEmpty) {
539      val btrd = busyTableRead.get
540      val bt = busyTable.get
541      btrd.io.in.fuBusyTable := bt
542      btrd.io.in.fuTypeRegVec := fuTypeVec
543      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
544    }
545    else {
546      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
547    }
548  }
549  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
550    if (busyTableRead.nonEmpty) {
551      val btrd = busyTableRead.get
552      val bt = busyTable.get
553      btrd.io.in.fuBusyTable := bt
554      btrd.io.in.fuTypeRegVec := fuTypeVec
555      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
556    }
557    else {
558      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
559    }
560  }
561
562  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
563    wakeUpQueueOption.foreach {
564      wakeUpQueue =>
565        val flush = Wire(new WakeupQueueFlush)
566        flush.redirect := io.flush
567        flush.ldCancel := io.ldCancel
568        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
569        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
570        wakeUpQueue.io.flush := flush
571        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
572        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
573        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
574        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
575    }
576  }
577
578  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
579    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
580    deq.bits.addrOH          := finalDeqSelOHVec(i)
581    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
582    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
583    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
584    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
585    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
586    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
587    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
588    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
589    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
590    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
591
592    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
593    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
594    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
595    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
596    deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i))
597    deq.bits.common.src := DontCare
598    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
599
600    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
601      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
602      rf.foreach(_.addr := psrc)
603      rf.foreach(_.srcType := srcType)
604    }
605    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
606      sink := source
607    }
608    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
609    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
610
611    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
612    deq.bits.common.perfDebugInfo.selectTime := GTimer()
613    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
614  }
615
616  private val deqShift = WireDefault(deqBeforeDly)
617  deqShift.zip(deqBeforeDly).foreach {
618    case (shifted, original) =>
619      original.ready := shifted.ready // this will not cause combinational loop
620      shifted.bits.common.loadDependency.foreach(
621        _ := original.bits.common.loadDependency.get.map(_ << 1)
622      )
623  }
624  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
625    NewPipelineConnect(
626      deq, deqDly, deqDly.valid,
627      false.B,
628      Option("Scheduler2DataPathPipe")
629    )
630  }
631  if(backendParams.debugEn) {
632    dontTouch(io.deqDelay)
633  }
634  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
635    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
636      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
637      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
638      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
639      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
640    } else if (wakeUpQueues(i).nonEmpty) {
641      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
642      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
643      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
644      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
645    } else {
646      wakeup.valid := false.B
647      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
648      wakeup.bits.is0Lat :=  0.U
649    }
650    if (wakeUpQueues(i).nonEmpty) {
651      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
652      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
653      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
654    }
655
656    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
657      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
658    }
659    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
660      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
661    }
662    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
663      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
664    }
665    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
666      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
667    }
668    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
669      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
670    }
671  }
672
673  // Todo: better counter implementation
674  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
675  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
676  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
677  private val enqEntryValidCntDeq0 = PopCount(
678    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
679  )
680  private val othersValidCntDeq0 = PopCount(
681    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
682  )
683  private val enqEntryValidCntDeq1 = PopCount(
684    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
685  )
686  private val othersValidCntDeq1 = PopCount(
687    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
688  )
689  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
690    io.enq.map(_.bits.fuType).map(fuType =>
691      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
692  }
693  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
694  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
695  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 +& enqValidCntDeq0 - deqBeforeDly.head.fire) // validCntDeqVec(0)
696  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 +& enqValidCntDeq1 - deqBeforeDly.last.fire) // validCntDeqVec(1)
697  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
698  for (i <- 0 until params.numEnq) {
699    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
700  }
701  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
702  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
703    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
704  }
705  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
706  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
707
708  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
709  io.status.empty := !Cat(validVec).orR
710  io.status.full := othersCanotIn
711  io.status.validCnt := PopCount(validVec)
712
713  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
714    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
715  }
716
717  // issue perf counter
718  // enq count
719  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
720  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
721  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
722  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
723  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
724  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
725  // valid count
726  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
727  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
728  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
729  // only split when more than 1 func type
730  if (params.getFuCfgs.size > 0) {
731    for (t <- FuType.functionNameMap.keys) {
732      val fuName = FuType.functionNameMap(t)
733      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
734        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
735      }
736    }
737  }
738  // ready instr count
739  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
740  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
741  // only split when more than 1 func type
742  if (params.getFuCfgs.size > 0) {
743    for (t <- FuType.functionNameMap.keys) {
744      val fuName = FuType.functionNameMap(t)
745      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
746        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
747      }
748    }
749  }
750
751  // deq instr count
752  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
753  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
754  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
755  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
756
757  // deq instr data source count
758  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
759    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
760  }.reduce(_ +& _))
761  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
762    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
763  }.reduce(_ +& _))
764  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
765    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
766  }.reduce(_ +& _))
767  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
768    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
769  }.reduce(_ +& _))
770
771  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
772    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
773  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
774  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
775    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
776  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
777  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
778    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
779  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
780  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
781    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
782  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
783
784  // deq instr data source count for each futype
785  for (t <- FuType.functionNameMap.keys) {
786    val fuName = FuType.functionNameMap(t)
787    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
788      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
789        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
790      }.reduce(_ +& _))
791      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
792        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
793      }.reduce(_ +& _))
794      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
795        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
796      }.reduce(_ +& _))
797      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
798        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
799      }.reduce(_ +& _))
800
801      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
802        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
803      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
804      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
805        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
806      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
807      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
808        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
809      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
810      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
811        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
812      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
813    }
814  }
815
816  // cancel instr count
817  if (params.hasIQWakeUp) {
818    val cancelVec: Vec[Bool] = entries.io.cancel.get
819    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
820    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
821    for (t <- FuType.functionNameMap.keys) {
822      val fuName = FuType.functionNameMap(t)
823      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
824        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
825        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
826      }
827    }
828  }
829}
830
831class IssueQueueJumpBundle extends Bundle {
832  val pc = UInt(VAddrData().dataWidth.W)
833}
834
835class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
836  val fastMatch = UInt(backendParams.LduCnt.W)
837  val fastImm = UInt(12.W)
838}
839
840class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
841
842class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
843  extends IssueQueueImp(wrapper)
844{
845  io.suggestName("none")
846  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
847
848  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
849    deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc)
850    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
851    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
852    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
853    deq.bits.common.predictInfo.foreach(x => {
854      x.target := DontCare
855      x.taken := deqEntryVec(i).bits.payload.pred_taken
856    })
857    // for std
858    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
859    // for i2f
860    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
861  }}
862}
863
864class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
865  extends IssueQueueImp(wrapper)
866{
867  s0_enqBits.foreach{ x =>
868    x.srcType(3) := SrcType.vp // v0: mask src
869    x.srcType(4) := SrcType.vp // vl&vtype
870  }
871  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
872    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
873    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
874    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
875    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
876  }}
877}
878
879class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
880  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
881  val checkWait = new Bundle {
882    val stIssuePtr = Input(new SqPtr)
883    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
884  }
885  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
886  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
887
888  // vector
889  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
890  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
891}
892
893class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
894  val memIO = Some(new IssueQueueMemBundle)
895}
896
897class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
898  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
899
900  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
901    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
902  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
903
904  io.suggestName("none")
905  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
906  private val memIO = io.memIO.get
907
908  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
909
910  for (i <- io.enq.indices) {
911    val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr)
912    val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => {
913      memIO.checkWait.memWaitUpdateReq.robIdx(i).valid &&
914        memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value
915    })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready
916    s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased
917  }
918
919  for (i <- entries.io.enq.indices) {
920    entries.io.enq(i).bits.status match { case enqData =>
921      enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
922      enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
923      enqData.mem.get.waitForStd := false.B
924      enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
925      enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
926      enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
927    }
928  }
929  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
930    slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid
931    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
932    slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
933    slowResp.bits.fuType := DontCare
934  }
935
936  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
937    fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid
938    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
939    fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
940    fastResp.bits.fuType := DontCare
941  }
942
943
944  entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
945  entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
946
947  // load wakeup
948  val loadWakeUpIter = memIO.loadWakeUp.iterator
949  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
950    if (param.hasLoadExu) {
951      require(wakeUpQueues(i).isEmpty)
952      val uop = loadWakeUpIter.next()
953
954      wakeup.valid := RegNext(uop.fire)
955      wakeup.bits.rfWen  := RegNext(uop.bits.rfWen  && uop.fire)
956      wakeup.bits.fpWen  := RegNext(uop.bits.fpWen  && uop.fire)
957      wakeup.bits.vecWen := RegNext(uop.bits.vecWen && uop.fire)
958      wakeup.bits.pdest  := RegNext(uop.bits.pdest)
959      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
960
961      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.rfWen  && uop.fire)))
962      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.fpWen  && uop.fire)))
963      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := RegNext(uop.bits.vecWen && uop.fire)))
964      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegNext(uop.bits.pdest)))
965      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
966
967      wakeup.bits.is0Lat := 0.U
968    }
969  }
970  require(!loadWakeUpIter.hasNext)
971
972  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
973    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
974    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
975    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
976    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
977    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
978    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
979    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
980    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
981    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
982  }
983}
984
985class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
986  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
987
988  require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
989  println(s"[IssueQueueVecMemImp] VstdCnt: ${params.VstdCnt}, VlduCnt: ${params.VlduCnt}, VstaCnt: ${params.VstaCnt}")
990
991  io.suggestName("none")
992  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
993  private val memIO = io.memIO.get
994
995  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
996
997  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
998    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
999    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
1000      (if (j < i) !valid(j) || compareVec(i)(j)
1001      else if (j == i) valid(i)
1002      else !valid(j) || !compareVec(j)(i))
1003    )).andR))
1004    resultOnehot
1005  }
1006
1007  val robIdxVec = entries.io.robIdx.get
1008  val uopIdxVec = entries.io.uopIdx.get
1009  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
1010
1011  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
1012  finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
1013
1014  if (params.isVecMemAddrIQ) {
1015    s0_enqBits.foreach{ x =>
1016      x.srcType(3) := SrcType.vp // v0: mask src
1017      x.srcType(4) := SrcType.vp // vl&vtype
1018    }
1019
1020    for (i <- io.enq.indices) {
1021      s0_enqBits(i).loadWaitBit := false.B
1022    }
1023
1024    for (i <- entries.io.enq.indices) {
1025      entries.io.enq(i).bits.status match { case enqData =>
1026        enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
1027        enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
1028        enqData.mem.get.waitForStd := false.B
1029        enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
1030        enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
1031        enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
1032      }
1033
1034      entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1035        slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1036        slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1037        slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1038        slowResp.bits.fuType := DontCare
1039      }
1040
1041      entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1042        fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1043        fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1044        fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1045        fastResp.bits.fuType           := DontCare
1046        fastResp.bits.uopIdx.get       := 0.U //todo
1047      }
1048
1049      entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
1050      entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
1051    }
1052  }
1053
1054  for (i <- entries.io.enq.indices) {
1055    entries.io.enq(i).bits.status.vecMem.get match {
1056      case enqData =>
1057        enqData.sqIdx := s0_enqBits(i).sqIdx
1058        enqData.lqIdx := s0_enqBits(i).lqIdx
1059    }
1060  }
1061
1062  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1063  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1064
1065
1066  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (resp, i) =>
1067    resp.bits.uopIdx.get := 0.U // Todo
1068  }
1069
1070  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1071    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
1072    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx)
1073    if (params.isVecLdAddrIQ) {
1074      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1075      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1076    }
1077    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1078    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1079    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1080    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1081  }
1082}
1083