1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 val IQValidNumVec = Output(MixedVec(backendParams.genIQValidNumBundle)) 53 54 val fromCtrlBlock = new Bundle { 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val vlWriteBack = new Bundle { 68 val vlIsZero = Input(Bool()) 69 val vlIsVlmax = Input(Bool()) 70 } 71 72 val fromSchedulers = new Bundle { 73 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 74 } 75 76 val toSchedulers = new Bundle { 77 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 78 } 79 80 val fromDataPath = new Bundle { 81 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 82 val og0Cancel = Input(ExuOH(backendParams.numExu)) 83 // Todo: remove this after no cancel signal from og1 84 val og1Cancel = Input(ExuOH(backendParams.numExu)) 85 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 86 // just be compatible to old code 87 def apply(i: Int)(j: Int) = resp(i)(j) 88 } 89 90 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 91 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 92 val vecLoadIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.VlduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 93 94 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 95 96 val memIO = if (params.isMemSchd) Some(new Bundle { 97 val lsqEnqIO = Flipped(new LsqEnqIO) 98 }) else None 99 val fromMem = if (params.isMemSchd) Some(new Bundle { 100 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 101 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 102 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 103 val vstuFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 104 val vlduFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 105 val stIssuePtr = Input(new SqPtr()) 106 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 107 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 108 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 109 val lqDeqPtr = Input(new LqPtr) 110 val sqDeqPtr = Input(new SqPtr) 111 // from lsq 112 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 113 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 114 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 115 }) else None 116 val toMem = if (params.isMemSchd) Some(new Bundle { 117 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 118 }) else None 119 val fromOg2 = if(params.isVfSchd) Some(MixedVec(params.issueBlockParams.map(x => Flipped(x.genOG2RespBundle)))) else None 120} 121 122abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 123 extends LazyModuleImp(wrapper) 124 with HasXSParameter 125{ 126 val io = IO(new SchedulerIO()) 127 128 // alias 129 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 130 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 131 private val schdType = params.schdType 132 133 // Modules 134 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 135 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 136 if (params.isIntSchd) { 137 dispatch2Iq.io.IQValidNumVec.get := io.IQValidNumVec 138 io.IQValidNumVec := MixedVecInit(issueQueues.map(_.io.validCntDeqVec)) 139 } 140 else io.IQValidNumVec := 0.U.asTypeOf(io.IQValidNumVec) 141 142 // valid count 143 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 144 145 // BusyTable Modules 146 val intBusyTable = schdType match { 147 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 148 case _ => None 149 } 150 151 val vfBusyTable = schdType match { 152 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 153 case _ => None 154 } 155 156 dispatch2Iq.io match { case dp2iq => 157 dp2iq.redirect <> io.fromCtrlBlock.flush 158 dp2iq.in <> io.fromDispatch.uops 159 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 160 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 161 } 162 163 intBusyTable match { 164 case Some(bt) => 165 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 166 btAllocPregs.valid := dpAllocPregs.isInt 167 btAllocPregs.bits := dpAllocPregs.preg 168 } 169 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 170 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 171 wb.bits := io.intWriteBack(i).addr 172 } 173 bt.io.wakeUp := io.fromSchedulers.wakeupVec 174 bt.io.cancel := io.fromDataPath.cancelToBusyTable 175 bt.io.ldCancel := io.ldCancel 176 case None => 177 } 178 179 vfBusyTable match { 180 case Some(bt) => 181 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 182 btAllocPregs.valid := dpAllocPregs.isFp 183 btAllocPregs.bits := dpAllocPregs.preg 184 } 185 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 186 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 187 wb.bits := io.vfWriteBack(i).addr 188 } 189 bt.io.wakeUp := io.fromSchedulers.wakeupVec 190 bt.io.cancel := io.fromDataPath.cancelToBusyTable 191 bt.io.ldCancel := io.ldCancel 192 case None => 193 } 194 195 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 196 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 197 198 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 199 sink.valid := source.wen 200 sink.bits.rfWen := source.intWen 201 sink.bits.fpWen := source.fpWen 202 sink.bits.vecWen := source.vecWen 203 sink.bits.pdest := source.addr 204 } 205 206 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 207 sink.valid := source.wen 208 sink.bits.rfWen := source.intWen 209 sink.bits.fpWen := source.fpWen 210 sink.bits.vecWen := source.vecWen 211 sink.bits.pdest := source.addr 212 } 213 214 // Connect bundles having the same wakeup source 215 issueQueues.zipWithIndex.foreach { case(iq, i) => 216 iq.io.wakeupFromIQ.foreach { wakeUp => 217 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 218 val exuIdx = wakeUp.bits.exuIdx 219 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 220 connectSamePort(wakeUp,wakeUpIn) 221 backendParams.connectWakeup(exuIdx) 222 if (backendParams.isCopyPdest(exuIdx)) { 223 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 224 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 225 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 226 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 227 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 228 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 229 } 230 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 231 if (iq.params.numVfSrc == 0) wakeUp.bits.fpWen := false.B 232 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 233 } 234 iq.io.og0Cancel := io.fromDataPath.og0Cancel 235 iq.io.og1Cancel := io.fromDataPath.og1Cancel 236 iq.io.ldCancel := io.ldCancel 237 } 238 239 // connect the vl writeback informatino to the issue queues 240 issueQueues.zipWithIndex.foreach { case(iq, i) => 241 iq.io.vlIsVlmax := io.vlWriteBack.vlIsVlmax 242 iq.io.vlIsZero := io.vlWriteBack.vlIsZero 243 } 244 245 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 246 issueQueues.flatMap(_.io.wakeupToIQ) 247 .map(x => (x.bits.exuIdx, x)) 248 .toMap 249 250 // Connect bundles having the same wakeup source 251 io.toSchedulers.wakeupVec.foreach { wakeUp => 252 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 253 } 254 255 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 256 toDpDy <> issueQueues(i).io.deqDelay 257 } 258 259 // Response 260 issueQueues.zipWithIndex.foreach { case (iq, i) => 261 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 262 og0Resp := io.fromDataPath(i)(j).og0resp 263 } 264 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 265 og1Resp := io.fromDataPath(i)(j).og1resp 266 } 267 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 268 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 269 finalIssueResp := io.loadFinalIssueResp(i)(j) 270 } else { 271 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 272 } 273 }) 274 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 275 if (io.memAddrIssueResp(i).isDefinedAt(j)) { 276 memAddrIssueResp := io.memAddrIssueResp(i)(j) 277 } else { 278 memAddrIssueResp := 0.U.asTypeOf(memAddrIssueResp) 279 } 280 }) 281 iq.io.vecLoadIssueResp.foreach(_.zipWithIndex.foreach { case (resp, deqIdx) => 282 resp := io.vecLoadIssueResp(i)(deqIdx) 283 }) 284 if(params.isVfSchd) { 285 iq.io.og2Resp.get.zipWithIndex.foreach { case (og2Resp, exuIdx) => 286 og2Resp := io.fromOg2.get(i)(exuIdx) 287 } 288 } 289 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 290 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 291 } 292 293 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 294 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 295 296 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 297 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 298} 299 300class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 301 extends SchedulerImpBase(wrapper) 302 with HasXSParameter 303{ 304// dontTouch(io.vfWbFuBusyTable) 305 println(s"[SchedulerArithImp] " + 306 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 307 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 308 309 issueQueues.zipWithIndex.foreach { case (iq, i) => 310 iq.io.flush <> io.fromCtrlBlock.flush 311 iq.io.enq <> dispatch2Iq.io.out(i) 312 val intWBIQ = params.schdType match { 313 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 314 case VfScheduler() => wakeupFromVfWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromVfWBPort.keys.toSeq.contains(x._2)).map(_._1) 315 case _ => null 316 } 317 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 318 } 319} 320 321// FIXME: Vector mem instructions may not be handled properly! 322class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 323 extends SchedulerImpBase(wrapper) 324 with HasXSParameter 325{ 326 println(s"[SchedulerMemImp] " + 327 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 328 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 329 330 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 331 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 332 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 333 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 334 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 335 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 336 337 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 338 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 339 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 340 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 341 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 342 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 343 344 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 345 346 private val loadWakeUp = issueQueues.filter(_.params.LdExuCnt > 0).map(_.asInstanceOf[IssueQueueMemAddrImp].io.memIO.get.loadWakeUp).flatten 347 require(loadWakeUp.length == io.fromMem.get.wakeup.length) 348 loadWakeUp.zip(io.fromMem.get.wakeup).foreach(x => x._1 := x._2) 349 350 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 351 iq.io.flush <> io.fromCtrlBlock.flush 352 iq.io.enq <> dispatch2Iq.io.out(i) 353 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromVfWBPort.keys.toSeq.contains(x._2)).map(_._1)).foreach{ case (sink, source) => sink := source} 354 } 355 356 ldAddrIQs.zipWithIndex.foreach { 357 case (imp: IssueQueueMemAddrImp, i) => 358 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 359 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 360 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 361 case _ => 362 } 363 364 stAddrIQs.zipWithIndex.foreach { 365 case (imp: IssueQueueMemAddrImp, i) => 366 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 367 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 368 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 369 case _ => 370 } 371 372 hyuIQs.zip(hyuIQIdxs).foreach { 373 case (imp: IssueQueueMemAddrImp, idx) => 374 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 375 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 376 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 377 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 378 // TODO: refactor ditry code 379 imp.io.deqDelay(1).ready := false.B 380 io.toDataPathAfterDelay(idx)(1).valid := false.B 381 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 382 case _ => 383 } 384 385 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 386 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 387 388 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 389 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 390 391 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 392 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 393 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 394 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 395 396 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 397 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 398 399 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 400 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 401 402 val d2IqStaOut = dispatch2Iq.io.out.zipWithIndex.filter(staIdxSeq contains _._2).unzip._1.flatten 403 d2IqStaOut.zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 404 val isAllReady = staIQ.ready && stdIQ.ready 405 dp.ready := isAllReady 406 staIQ.valid := dp.valid && isAllReady 407 stdIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 408 } 409 410 val d2IqHyaOut = dispatch2Iq.io.out.zipWithIndex.filter(hyaIdxSeq contains _._2).unzip._1.flatten 411 d2IqHyaOut.zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 412 val isAllReady = hyaIQ.ready && hydIQ.ready 413 dp.ready := isAllReady 414 hyaIQ.valid := dp.valid && isAllReady 415 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 416 } 417 418 stDataIQs.zipWithIndex.foreach { case (iq, i) => 419 iq.io.flush <> io.fromCtrlBlock.flush 420 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromVfWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq).foreach{ case (sink, source) => sink := source} 421 } 422 423 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 424 stdIQEnq.bits := staIQEnq.bits 425 // Store data reuses store addr src(1) in dispatch2iq 426 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 427 // \ 428 // ---src*(1)--> [stdIQ] 429 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 430 // instead of dispatch2Iq.io.out(x).bits.src*(1) 431 val stdIdx = 1 432 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 433 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 434 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 435 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 436 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 437 } 438 439 vecMemIQs.foreach { 440 case imp: IssueQueueVecMemImp => 441 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 442 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 443 // not used 444 //imp.io.memIO.get.feedbackIO.head := io.fromMem.get.vstuFeedback.head // only vector store replay 445 // maybe not used 446 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 447 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 448 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromVfWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq).foreach{ case (sink, source) => sink := source} 449 450 case _ => 451 } 452 val vecMemFeedbackIO: Seq[MemRSFeedbackIO] = vecMemIQs.map { 453 case imp: IssueQueueVecMemImp => 454 imp.io.memIO.get.feedbackIO 455 }.flatten 456 assert(vecMemFeedbackIO.size == io.fromMem.get.vstuFeedback.size, "vecMemFeedback size dont match!") 457 vecMemFeedbackIO.zip(io.fromMem.get.vstuFeedback).foreach{ 458 case (sink, source) => 459 sink := source 460 } 461 462 val lsqEnqCtrl = Module(new LsqEnqCtrl) 463 464 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 465 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 466 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 467 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 468 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 469 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 470 dispatch2Iq.io.lqFreeCount.get := lsqEnqCtrl.io.lqFreeCount 471 dispatch2Iq.io.sqFreeCount.get := lsqEnqCtrl.io.sqFreeCount 472 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 473 474 dontTouch(io.vecLoadIssueResp) 475} 476