1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35import scala.collection.Seq 36import chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 37 38class indexedLSUopTable(uopIdx:Int) extends Module { 39 val src = IO(Input(UInt(7.W))) 40 val outOffsetVs2 = IO(Output(UInt(3.W))) 41 val outOffsetVd = IO(Output(UInt(3.W))) 42 val outIsFirstUopInVd = IO(Output(Bool())) 43 def genCsBundle_VEC_INDEXED_LDST(lmul:Int, emul:Int, nfields:Int, uopIdx:Int): (Int, Int, Int) ={ 44 if (lmul * nfields <= 8) { 45 for (k <-0 until nfields) { 46 if (lmul < emul) { // lmul < emul, uop num is depend on emul * nf 47 var offset = 1 << (emul - lmul) 48 for (i <- 0 until (1 << emul)) { 49 if (uopIdx == k * (1 << emul) + i) { 50 return (i, i / offset + k * (1 << lmul), if (i % offset == 0) 1 else 0) 51 } 52 } 53 } else { // lmul > emul, uop num is depend on lmul * nf 54 var offset = 1 << (lmul - emul) 55 for (i <- 0 until (1 << lmul)) { 56 if (uopIdx == k * (1 << lmul) + i) { 57 return (i / offset, i + k * (1 << lmul), 1) 58 } 59 } 60 } 61 } 62 } 63 return (0, 0, 1) 64 } 65 // strided load/store 66 var combVemulNf : Seq[(Int, Int, Int, Int, Int, Int)] = Seq() 67 for (emul <- 0 until 4) { 68 for (lmul <- 0 until 4) { 69 for (nf <- 0 until 8) { 70 var offset = genCsBundle_VEC_INDEXED_LDST(lmul, emul, nf+1, uopIdx) 71 var offsetVs2 = offset._1 72 var offsetVd = offset._2 73 var isFirstUopInVd = offset._3 74 combVemulNf :+= (emul, lmul, nf, isFirstUopInVd, offsetVs2, offsetVd) 75 } 76 } 77 } 78 val out = decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 79 case (emul, lmul, nf, isFirstUopInVd, offsetVs2, offsetVd) => 80 (BitPat((emul << 5 | lmul << 3 | nf).U(7.W)), BitPat((isFirstUopInVd << 6 | offsetVs2 << 3 | offsetVd).U(7.W))) 81 }, BitPat.N(7))) 82 outOffsetVs2 := out(5, 3) 83 outOffsetVd := out(2, 0) 84 outIsFirstUopInVd := out(6).asBool 85} 86 87trait VectorConstants { 88 val MAX_VLMUL = 8 89 val FP_TMP_REG_MV = 32 90 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 91 val MAX_INDEXED_LS_UOPNUM = 64 92} 93 94class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 95 val redirect = Input(Bool()) 96 val csrCtrl = Input(new CustomCSRCtrlIO) 97 // When the first inst in decode vector is complex inst, pass it in 98 val in = Flipped(DecoupledIO(new Bundle { 99 val simpleDecodedInst = new DecodedInst 100 val uopInfo = new UopInfo 101 })) 102 val out = new Bundle { 103 val complexDecodedInsts = Vec(RenameWidth, DecoupledIO(new DecodedInst)) 104 } 105 val complexNum = Output(UInt(3.W)) 106} 107 108/** 109 * @author zly 110 */ 111class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 112 val io = IO(new DecodeUnitCompIO) 113 114 // alias 115 private val inReady = io.in.ready 116 private val inValid = io.in.valid 117 private val inDecodedInst = WireInit(io.in.bits.simpleDecodedInst) 118 private val inInstFields = io.in.bits.simpleDecodedInst.instr.asTypeOf(new XSInstBitFields) 119 private val inUopInfo = io.in.bits.uopInfo 120 private val outValids = io.out.complexDecodedInsts.map(_.valid) 121 private val outReadys = io.out.complexDecodedInsts.map(_.ready) 122 private val outDecodedInsts = io.out.complexDecodedInsts.map(_.bits) 123 private val outComplexNum = io.complexNum 124 125 val maxUopSize = MaxUopSize 126 when (io.in.fire && io.in.bits.simpleDecodedInst.isVset) { 127 when(inInstFields.RD === 0.U && inInstFields.RS1 === 0.U) { 128 inDecodedInst.fuOpType := VSETOpType.keepVl(io.in.bits.simpleDecodedInst.fuOpType) 129 }.elsewhen(inInstFields.RS1 === 0.U) { 130 inDecodedInst.fuOpType := VSETOpType.setVlmax(io.in.bits.simpleDecodedInst.fuOpType) 131 } 132 } 133 134 val latchedInst = RegEnable(inDecodedInst, inValid && inReady) 135 val latchedUopInfo = RegEnable(inUopInfo, inValid && inReady) 136 //input bits 137 private val instFields: XSInstBitFields = latchedInst.instr.asTypeOf(new XSInstBitFields) 138 139 val src1 = Cat(0.U(1.W), instFields.RS1) 140 val src2 = Cat(0.U(1.W), instFields.RS2) 141 val dest = Cat(0.U(1.W), instFields.RD) 142 143 val nf = instFields.NF 144 val width = instFields.WIDTH(1, 0) 145 146 //output of DecodeUnit 147 val numOfUop = Wire(UInt(log2Up(maxUopSize).W)) 148 val numOfWB = Wire(UInt(log2Up(maxUopSize).W)) 149 val lmul = Wire(UInt(4.W)) 150 val isVsetSimple = Wire(Bool()) 151 152 val indexedLSRegOffset = Seq.tabulate(MAX_INDEXED_LS_UOPNUM)(i => Module(new indexedLSUopTable(i))) 153 indexedLSRegOffset.map(_.src := 0.U) 154 155 //pre decode 156 lmul := latchedUopInfo.lmul 157 isVsetSimple := latchedInst.isVset 158 val vlmulReg = latchedInst.vpu.vlmul 159 val vsewReg = latchedInst.vpu.vsew 160 161 //Type of uop Div 162 val typeOfSplit = latchedInst.uopSplitType 163 val src1Type = latchedInst.srcType(0) 164 val src1IsImm = src1Type === SrcType.imm 165 166 numOfUop := latchedUopInfo.numOfUop 167 numOfWB := latchedUopInfo.numOfWB 168 169 //uops dispatch 170 val s_idle :: s_active :: Nil = Enum(2) 171 val state = RegInit(s_idle) 172 val stateNext = WireDefault(state) 173 val numDecodedUop = RegInit(0.U(log2Up(maxUopSize).W)) 174 val uopRes = RegInit(0.U(log2Up(maxUopSize).W)) 175 val uopResNext = WireInit(uopRes) 176 177 //uop div up to maxUopSize 178 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 179 csBundle.foreach { case dst => 180 dst := latchedInst 181 dst.numUops := latchedUopInfo.numOfUop 182 dst.numWB := latchedUopInfo.numOfWB 183 dst.firstUop := false.B 184 dst.lastUop := false.B 185 } 186 187 csBundle(0).firstUop := true.B 188 csBundle(numOfUop - 1.U).lastUop := true.B 189 190 switch(typeOfSplit) { 191 is(UopSplitType.VSET) { 192 // In simple decoder, rfWen and vecWen are not set 193 when(isVsetSimple) { 194 // Default 195 // uop0 set rd, never flushPipe 196 csBundle(0).fuType := FuType.vsetiwi.U 197 csBundle(0).flushPipe := false.B 198 csBundle(0).rfWen := true.B 199 // uop1 set vl, vsetvl will flushPipe 200 csBundle(1).ldest := VCONFIG_IDX.U 201 csBundle(1).vecWen := true.B 202 when(VSETOpType.isVsetvli(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 203 csBundle(1).fuType := FuType.vsetfwf.U 204 csBundle(1).srcType(0) := SrcType.vp 205 csBundle(1).lsrc(0) := VCONFIG_IDX.U 206 }.elsewhen(VSETOpType.isVsetvl(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 207 // uop0: mv vtype gpr to vector region 208 csBundle(0).srcType(0) := SrcType.xp 209 csBundle(0).srcType(1) := SrcType.no 210 csBundle(0).lsrc(1) := 0.U 211 csBundle(0).ldest := FP_TMP_REG_MV.U 212 csBundle(0).fuType := FuType.i2f.U 213 csBundle(0).fpWen := true.B 214 csBundle(0).fpu.isAddSub := false.B 215 csBundle(0).fpu.typeTagIn := FPU.D 216 csBundle(0).fpu.typeTagOut := FPU.D 217 csBundle(0).fpu.fromInt := true.B 218 csBundle(0).fpu.wflags := false.B 219 csBundle(0).fpu.fpWen := true.B 220 csBundle(0).fpu.div := false.B 221 csBundle(0).fpu.sqrt := false.B 222 csBundle(0).fpu.fcvt := false.B 223 csBundle(0).flushPipe := false.B 224 // uop1: uvsetvcfg_vv 225 csBundle(1).fuType := FuType.vsetfwf.U 226 // vl 227 csBundle(1).srcType(0) := SrcType.vp 228 csBundle(1).lsrc(0) := VCONFIG_IDX.U 229 // vtype 230 csBundle(1).srcType(1) := SrcType.fp 231 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 232 csBundle(1).vecWen := true.B 233 csBundle(1).ldest := VCONFIG_IDX.U 234 } 235 } 236 } 237 is(UopSplitType.VEC_VVV) { 238 for (i <- 0 until MAX_VLMUL) { 239 csBundle(i).lsrc(0) := src1 + i.U 240 csBundle(i).lsrc(1) := src2 + i.U 241 csBundle(i).lsrc(2) := dest + i.U 242 csBundle(i).ldest := dest + i.U 243 csBundle(i).uopIdx := i.U 244 } 245 } 246 is(UopSplitType.VEC_VFV) { 247 for (i <- 0 until MAX_VLMUL) { 248 csBundle(i).lsrc(1) := src2 + i.U 249 csBundle(i).lsrc(2) := dest + i.U 250 csBundle(i).ldest := dest + i.U 251 csBundle(i).uopIdx := i.U 252 } 253 } 254 is(UopSplitType.VEC_EXT2) { 255 for (i <- 0 until MAX_VLMUL / 2) { 256 csBundle(2 * i).lsrc(1) := src2 + i.U 257 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 258 csBundle(2 * i).ldest := dest + (2 * i).U 259 csBundle(2 * i).uopIdx := (2 * i).U 260 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 261 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 262 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 263 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 264 } 265 } 266 is(UopSplitType.VEC_EXT4) { 267 for (i <- 0 until MAX_VLMUL / 4) { 268 csBundle(4 * i).lsrc(1) := src2 + i.U 269 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 270 csBundle(4 * i).ldest := dest + (4 * i).U 271 csBundle(4 * i).uopIdx := (4 * i).U 272 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 273 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 274 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 275 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 276 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 277 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 278 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 279 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 280 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 281 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 282 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 283 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 284 } 285 } 286 is(UopSplitType.VEC_EXT8) { 287 for (i <- 0 until MAX_VLMUL) { 288 csBundle(i).lsrc(1) := src2 289 csBundle(i).lsrc(2) := dest + i.U 290 csBundle(i).ldest := dest + i.U 291 csBundle(i).uopIdx := i.U 292 } 293 } 294 is(UopSplitType.VEC_0XV) { 295 /* 296 FMV.D.X 297 */ 298 csBundle(0).srcType(0) := SrcType.reg 299 csBundle(0).srcType(1) := SrcType.imm 300 csBundle(0).lsrc(1) := 0.U 301 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 302 csBundle(0).fuType := FuType.i2v.U 303 csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), vsewReg) 304 csBundle(0).rfWen := false.B 305 csBundle(0).fpWen := false.B 306 csBundle(0).vecWen := true.B 307 /* 308 vmv.s.x 309 */ 310 csBundle(1).srcType(0) := SrcType.vp 311 csBundle(1).srcType(1) := SrcType.imm 312 csBundle(1).srcType(2) := SrcType.vp 313 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 314 csBundle(1).lsrc(1) := 0.U 315 csBundle(1).lsrc(2) := dest 316 csBundle(1).ldest := dest 317 csBundle(1).rfWen := false.B 318 csBundle(1).fpWen := false.B 319 csBundle(1).vecWen := true.B 320 csBundle(1).uopIdx := 0.U 321 } 322 is(UopSplitType.VEC_VXV) { 323 /* 324 i to vector move 325 */ 326 csBundle(0).srcType(0) := SrcType.reg 327 csBundle(0).srcType(1) := SrcType.imm 328 csBundle(0).lsrc(1) := 0.U 329 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 330 csBundle(0).fuType := FuType.i2v.U 331 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 332 csBundle(0).vecWen := true.B 333 /* 334 LMUL 335 */ 336 for (i <- 0 until MAX_VLMUL) { 337 csBundle(i + 1).srcType(0) := SrcType.vp 338 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 339 csBundle(i + 1).lsrc(1) := src2 + i.U 340 csBundle(i + 1).lsrc(2) := dest + i.U 341 csBundle(i + 1).ldest := dest + i.U 342 csBundle(i + 1).uopIdx := i.U 343 } 344 } 345 is(UopSplitType.VEC_VVW) { 346 for (i <- 0 until MAX_VLMUL / 2) { 347 csBundle(2 * i).lsrc(0) := src1 + i.U 348 csBundle(2 * i).lsrc(1) := src2 + i.U 349 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 350 csBundle(2 * i).ldest := dest + (2 * i).U 351 csBundle(2 * i).uopIdx := (2 * i).U 352 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 353 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 354 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 355 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 356 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 357 } 358 } 359 is(UopSplitType.VEC_VFW) { 360 for (i <- 0 until MAX_VLMUL / 2) { 361 csBundle(2 * i).lsrc(0) := src1 362 csBundle(2 * i).lsrc(1) := src2 + i.U 363 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 364 csBundle(2 * i).ldest := dest + (2 * i).U 365 csBundle(2 * i).uopIdx := (2 * i).U 366 csBundle(2 * i + 1).lsrc(0) := src1 367 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 368 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 369 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 370 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 371 } 372 } 373 is(UopSplitType.VEC_WVW) { 374 for (i <- 0 until MAX_VLMUL / 2) { 375 csBundle(2 * i).lsrc(0) := src1 + i.U 376 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 377 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 378 csBundle(2 * i).ldest := dest + (2 * i).U 379 csBundle(2 * i).uopIdx := (2 * i).U 380 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 381 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 382 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 383 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 384 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 385 } 386 } 387 is(UopSplitType.VEC_VXW) { 388 /* 389 i to vector move 390 */ 391 csBundle(0).srcType(0) := SrcType.reg 392 csBundle(0).srcType(1) := SrcType.imm 393 csBundle(0).lsrc(1) := 0.U 394 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 395 csBundle(0).fuType := FuType.i2v.U 396 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 397 csBundle(0).vecWen := true.B 398 399 for (i <- 0 until MAX_VLMUL / 2) { 400 csBundle(2 * i + 1).srcType(0) := SrcType.vp 401 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 402 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 403 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 404 csBundle(2 * i + 1).ldest := dest + (2 * i).U 405 csBundle(2 * i + 1).uopIdx := (2 * i).U 406 csBundle(2 * i + 2).srcType(0) := SrcType.vp 407 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 408 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 409 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 410 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 411 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 412 } 413 } 414 is(UopSplitType.VEC_WXW) { 415 /* 416 i to vector move 417 */ 418 csBundle(0).srcType(0) := SrcType.reg 419 csBundle(0).srcType(1) := SrcType.imm 420 csBundle(0).lsrc(1) := 0.U 421 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 422 csBundle(0).fuType := FuType.i2v.U 423 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 424 csBundle(0).vecWen := true.B 425 426 for (i <- 0 until MAX_VLMUL / 2) { 427 csBundle(2 * i + 1).srcType(0) := SrcType.vp 428 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 429 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 430 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 431 csBundle(2 * i + 1).ldest := dest + (2 * i).U 432 csBundle(2 * i + 1).uopIdx := (2 * i).U 433 csBundle(2 * i + 2).srcType(0) := SrcType.vp 434 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 435 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 436 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 437 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 438 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 439 } 440 } 441 is(UopSplitType.VEC_WVV) { 442 for (i <- 0 until MAX_VLMUL / 2) { 443 444 csBundle(2 * i).lsrc(0) := src1 + i.U 445 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 446 csBundle(2 * i).lsrc(2) := dest + i.U 447 csBundle(2 * i).ldest := dest + i.U 448 csBundle(2 * i).uopIdx := (2 * i).U 449 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 450 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 451 csBundle(2 * i + 1).lsrc(2) := dest + i.U 452 csBundle(2 * i + 1).ldest := dest + i.U 453 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 454 } 455 } 456 is(UopSplitType.VEC_WFW) { 457 for (i <- 0 until MAX_VLMUL / 2) { 458 csBundle(2 * i).lsrc(0) := src1 459 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 460 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 461 csBundle(2 * i).ldest := dest + (2 * i).U 462 csBundle(2 * i).uopIdx := (2 * i).U 463 csBundle(2 * i + 1).lsrc(0) := src1 464 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 465 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 466 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 467 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 468 } 469 } 470 is(UopSplitType.VEC_WXV) { 471 /* 472 i to vector move 473 */ 474 csBundle(0).srcType(0) := SrcType.reg 475 csBundle(0).srcType(1) := SrcType.imm 476 csBundle(0).lsrc(1) := 0.U 477 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 478 csBundle(0).fuType := FuType.i2v.U 479 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 480 csBundle(0).vecWen := true.B 481 482 for (i <- 0 until MAX_VLMUL / 2) { 483 csBundle(2 * i + 1).srcType(0) := SrcType.vp 484 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 485 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 486 csBundle(2 * i + 1).lsrc(2) := dest + i.U 487 csBundle(2 * i + 1).ldest := dest + i.U 488 csBundle(2 * i + 1).uopIdx := (2 * i).U 489 csBundle(2 * i + 2).srcType(0) := SrcType.vp 490 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 491 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 492 csBundle(2 * i + 2).lsrc(2) := dest + i.U 493 csBundle(2 * i + 2).ldest := dest + i.U 494 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 495 } 496 } 497 is(UopSplitType.VEC_VVM) { 498 csBundle(0).lsrc(2) := dest 499 csBundle(0).ldest := dest 500 csBundle(0).uopIdx := 0.U 501 for (i <- 1 until MAX_VLMUL) { 502 csBundle(i).lsrc(0) := src1 + i.U 503 csBundle(i).lsrc(1) := src2 + i.U 504 csBundle(i).lsrc(2) := dest 505 csBundle(i).ldest := dest 506 csBundle(i).uopIdx := i.U 507 } 508 } 509 is(UopSplitType.VEC_VFM) { 510 csBundle(0).lsrc(2) := dest 511 csBundle(0).ldest := dest 512 csBundle(0).uopIdx := 0.U 513 for (i <- 1 until MAX_VLMUL) { 514 csBundle(i).lsrc(0) := src1 515 csBundle(i).lsrc(1) := src2 + i.U 516 csBundle(i).lsrc(2) := dest 517 csBundle(i).ldest := dest 518 csBundle(i).uopIdx := i.U 519 } 520 csBundle(numOfUop - 1.U).ldest := dest 521 } 522 is(UopSplitType.VEC_VXM) { 523 /* 524 i to vector move 525 */ 526 csBundle(0).srcType(0) := SrcType.reg 527 csBundle(0).srcType(1) := SrcType.imm 528 csBundle(0).lsrc(1) := 0.U 529 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 530 csBundle(0).fuType := FuType.i2v.U 531 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 532 csBundle(0).vecWen := true.B 533 //LMUL 534 csBundle(1).srcType(0) := SrcType.vp 535 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 536 csBundle(1).lsrc(2) := dest 537 csBundle(1).ldest := dest 538 csBundle(1).uopIdx := 0.U 539 for (i <- 1 until MAX_VLMUL) { 540 csBundle(i + 1).srcType(0) := SrcType.vp 541 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 542 csBundle(i + 1).lsrc(1) := src2 + i.U 543 csBundle(i + 1).lsrc(2) := dest 544 csBundle(i + 1).ldest := dest 545 csBundle(i + 1).uopIdx := i.U 546 } 547 csBundle(numOfUop - 1.U).ldest := dest 548 } 549 is(UopSplitType.VEC_SLIDE1UP) { 550 /* 551 i to vector move 552 */ 553 csBundle(0).srcType(0) := SrcType.reg 554 csBundle(0).srcType(1) := SrcType.imm 555 csBundle(0).lsrc(1) := 0.U 556 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 557 csBundle(0).fuType := FuType.i2v.U 558 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 559 csBundle(0).vecWen := true.B 560 //LMUL 561 csBundle(1).srcType(0) := SrcType.vp 562 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 563 csBundle(1).lsrc(2) := dest 564 csBundle(1).ldest := dest 565 csBundle(1).uopIdx := 0.U 566 for (i <- 1 until MAX_VLMUL) { 567 csBundle(i + 1).srcType(0) := SrcType.vp 568 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 569 csBundle(i + 1).lsrc(1) := src2 + i.U 570 csBundle(i + 1).lsrc(2) := dest + i.U 571 csBundle(i + 1).ldest := dest + i.U 572 csBundle(i + 1).uopIdx := i.U 573 } 574 } 575 is(UopSplitType.VEC_FSLIDE1UP) { 576 //LMUL 577 csBundle(0).srcType(0) := SrcType.fp 578 csBundle(0).lsrc(0) := src1 579 csBundle(0).lsrc(1) := src2 580 csBundle(0).lsrc(2) := dest 581 csBundle(0).ldest := dest 582 csBundle(0).uopIdx := 0.U 583 for (i <- 1 until MAX_VLMUL) { 584 csBundle(i).srcType(0) := SrcType.vp 585 csBundle(i).lsrc(0) := src2 + (i - 1).U 586 csBundle(i).lsrc(1) := src2 + i.U 587 csBundle(i).lsrc(2) := dest + i.U 588 csBundle(i).ldest := dest + i.U 589 csBundle(i).uopIdx := i.U 590 } 591 } 592 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 593 /* 594 i to vector move 595 */ 596 csBundle(0).srcType(0) := SrcType.reg 597 csBundle(0).srcType(1) := SrcType.imm 598 csBundle(0).lsrc(1) := 0.U 599 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 600 csBundle(0).fuType := FuType.i2v.U 601 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 602 csBundle(0).vecWen := true.B 603 //LMUL 604 for (i <- 0 until MAX_VLMUL) { 605 csBundle(2 * i + 1).srcType(0) := SrcType.vp 606 csBundle(2 * i + 1).srcType(1) := SrcType.vp 607 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 608 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 609 csBundle(2 * i + 1).lsrc(2) := dest + i.U 610 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 611 csBundle(2 * i + 1).uopIdx := (2 * i).U 612 if (2 * i + 2 < MAX_VLMUL * 2) { 613 csBundle(2 * i + 2).srcType(0) := SrcType.vp 614 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 615 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 616 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 617 csBundle(2 * i + 2).ldest := dest + i.U 618 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 619 } 620 } 621 csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 622 csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 623 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 624 } 625 is(UopSplitType.VEC_FSLIDE1DOWN) { 626 //LMUL 627 for (i <- 0 until MAX_VLMUL) { 628 csBundle(2 * i).srcType(0) := SrcType.vp 629 csBundle(2 * i).srcType(1) := SrcType.vp 630 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 631 csBundle(2 * i).lsrc(1) := src2 + i.U 632 csBundle(2 * i).lsrc(2) := dest + i.U 633 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 634 csBundle(2 * i).uopIdx := (2 * i).U 635 csBundle(2 * i + 1).srcType(0) := SrcType.fp 636 csBundle(2 * i + 1).lsrc(0) := src1 637 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 638 csBundle(2 * i + 1).ldest := dest + i.U 639 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 640 } 641 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 642 csBundle(numOfUop - 1.U).lsrc(0) := src1 643 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 644 } 645 is(UopSplitType.VEC_VRED) { 646 when(vlmulReg === "b001".U) { 647 csBundle(0).srcType(2) := SrcType.DC 648 csBundle(0).lsrc(0) := src2 + 1.U 649 csBundle(0).lsrc(1) := src2 650 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 651 csBundle(0).uopIdx := 0.U 652 } 653 when(vlmulReg === "b010".U) { 654 csBundle(0).srcType(2) := SrcType.DC 655 csBundle(0).lsrc(0) := src2 + 1.U 656 csBundle(0).lsrc(1) := src2 657 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 658 csBundle(0).uopIdx := 0.U 659 660 csBundle(1).srcType(2) := SrcType.DC 661 csBundle(1).lsrc(0) := src2 + 3.U 662 csBundle(1).lsrc(1) := src2 + 2.U 663 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 664 csBundle(1).uopIdx := 1.U 665 666 csBundle(2).srcType(2) := SrcType.DC 667 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 668 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 669 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 670 csBundle(2).uopIdx := 2.U 671 } 672 when(vlmulReg === "b011".U) { 673 for (i <- 0 until MAX_VLMUL) { 674 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 675 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 676 csBundle(i).lsrc(1) := src2 + (i * 2).U 677 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 678 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 679 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 680 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 681 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 682 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 683 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 684 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 685 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 686 } 687 csBundle(i).srcType(2) := SrcType.DC 688 csBundle(i).uopIdx := i.U 689 } 690 } 691 when(vlmulReg(2) === 0.U && vlmulReg(1, 0).orR) { 692 /* 693 * 2 <= vlmul <= 8 694 */ 695 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 696 csBundle(numOfUop - 1.U).lsrc(0) := src1 697 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 698 csBundle(numOfUop - 1.U).lsrc(2) := dest 699 csBundle(numOfUop - 1.U).ldest := dest 700 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 701 } 702 } 703 is(UopSplitType.VEC_VFRED) { 704 val vlmul = vlmulReg 705 val vsew = vsewReg 706 when(vlmul === VLmul.m8){ 707 for (i <- 0 until 4) { 708 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 709 csBundle(i).lsrc(1) := src2 + (i * 2).U 710 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 711 csBundle(i).uopIdx := i.U 712 } 713 for (i <- 4 until 6) { 714 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 715 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 716 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 717 csBundle(i).uopIdx := i.U 718 } 719 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 720 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 721 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 722 csBundle(6).uopIdx := 6.U 723 when(vsew === VSew.e64) { 724 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 725 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 726 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 727 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 728 csBundle(7).uopIdx := 7.U 729 csBundle(8).lsrc(0) := src1 730 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 731 csBundle(8).ldest := dest 732 csBundle(8).uopIdx := 8.U 733 } 734 when(vsew === VSew.e32) { 735 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 736 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 737 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 738 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 739 csBundle(7).uopIdx := 7.U 740 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 741 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 742 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 743 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 744 csBundle(8).uopIdx := 8.U 745 csBundle(9).lsrc(0) := src1 746 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 747 csBundle(9).ldest := dest 748 csBundle(9).uopIdx := 9.U 749 } 750 when(vsew === VSew.e16) { 751 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 752 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 753 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 754 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 755 csBundle(7).uopIdx := 7.U 756 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 757 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 758 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 759 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 760 csBundle(8).uopIdx := 8.U 761 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 762 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 763 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 764 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 765 csBundle(9).uopIdx := 9.U 766 csBundle(10).lsrc(0) := src1 767 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 768 csBundle(10).ldest := dest 769 csBundle(10).uopIdx := 10.U 770 } 771 } 772 when(vlmul === VLmul.m4) { 773 for (i <- 0 until 2) { 774 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 775 csBundle(i).lsrc(1) := src2 + (i * 2).U 776 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 777 csBundle(i).uopIdx := i.U 778 } 779 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 780 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 781 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 782 csBundle(2).uopIdx := 2.U 783 when(vsew === VSew.e64) { 784 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 785 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 786 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 787 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 788 csBundle(3).uopIdx := 3.U 789 csBundle(4).lsrc(0) := src1 790 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 791 csBundle(4).ldest := dest 792 csBundle(4).uopIdx := 4.U 793 } 794 when(vsew === VSew.e32) { 795 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 796 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 797 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 798 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 799 csBundle(3).uopIdx := 3.U 800 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 801 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 802 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 803 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 804 csBundle(4).uopIdx := 4.U 805 csBundle(5).lsrc(0) := src1 806 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 807 csBundle(5).ldest := dest 808 csBundle(5).uopIdx := 5.U 809 } 810 when(vsew === VSew.e16) { 811 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 812 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 813 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 814 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 815 csBundle(3).uopIdx := 3.U 816 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 817 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 818 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 819 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 820 csBundle(4).uopIdx := 4.U 821 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 822 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 823 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 824 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 825 csBundle(5).uopIdx := 5.U 826 csBundle(6).lsrc(0) := src1 827 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 828 csBundle(6).ldest := dest 829 csBundle(6).uopIdx := 6.U 830 } 831 } 832 when(vlmul === VLmul.m2) { 833 csBundle(0).lsrc(0) := src2 + 1.U 834 csBundle(0).lsrc(1) := src2 + 0.U 835 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 836 csBundle(0).uopIdx := 0.U 837 when(vsew === VSew.e64) { 838 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 839 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 840 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 841 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 842 csBundle(1).uopIdx := 1.U 843 csBundle(2).lsrc(0) := src1 844 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 845 csBundle(2).ldest := dest 846 csBundle(2).uopIdx := 2.U 847 } 848 when(vsew === VSew.e32) { 849 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 850 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 851 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 852 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 853 csBundle(1).uopIdx := 1.U 854 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 855 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 856 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 857 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 858 csBundle(2).uopIdx := 2.U 859 csBundle(3).lsrc(0) := src1 860 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 861 csBundle(3).ldest := dest 862 csBundle(3).uopIdx := 3.U 863 } 864 when(vsew === VSew.e16) { 865 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 866 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 867 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 868 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 869 csBundle(1).uopIdx := 1.U 870 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 871 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 872 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 873 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 874 csBundle(2).uopIdx := 2.U 875 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 876 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 877 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 878 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 879 csBundle(3).uopIdx := 3.U 880 csBundle(4).lsrc(0) := src1 881 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 882 csBundle(4).ldest := dest 883 csBundle(4).uopIdx := 4.U 884 } 885 } 886 when(vlmul === VLmul.m1) { 887 when(vsew === VSew.e64) { 888 csBundle(0).lsrc(0) := src2 889 csBundle(0).lsrc(1) := src2 890 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 891 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 892 csBundle(0).uopIdx := 0.U 893 csBundle(1).lsrc(0) := src1 894 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 895 csBundle(1).ldest := dest 896 csBundle(1).uopIdx := 1.U 897 } 898 when(vsew === VSew.e32) { 899 csBundle(0).lsrc(0) := src2 900 csBundle(0).lsrc(1) := src2 901 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 902 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 903 csBundle(0).uopIdx := 0.U 904 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 905 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 906 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 907 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 908 csBundle(1).uopIdx := 1.U 909 csBundle(2).lsrc(0) := src1 910 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 911 csBundle(2).ldest := dest 912 csBundle(2).uopIdx := 2.U 913 } 914 when(vsew === VSew.e16) { 915 csBundle(0).lsrc(0) := src2 916 csBundle(0).lsrc(1) := src2 917 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 918 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 919 csBundle(0).uopIdx := 0.U 920 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 921 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 922 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 923 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 924 csBundle(1).uopIdx := 1.U 925 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 926 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 927 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 928 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 929 csBundle(2).uopIdx := 2.U 930 csBundle(3).lsrc(0) := src1 931 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 932 csBundle(3).ldest := dest 933 csBundle(3).uopIdx := 3.U 934 } 935 } 936 when(vlmul === VLmul.mf2) { 937 when(vsew === VSew.e32) { 938 csBundle(0).lsrc(0) := src2 939 csBundle(0).lsrc(1) := src2 940 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 941 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 942 csBundle(0).uopIdx := 0.U 943 csBundle(1).lsrc(0) := src1 944 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 945 csBundle(1).ldest := dest 946 csBundle(1).uopIdx := 1.U 947 } 948 when(vsew === VSew.e16) { 949 csBundle(0).lsrc(0) := src2 950 csBundle(0).lsrc(1) := src2 951 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 952 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 953 csBundle(0).uopIdx := 0.U 954 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 955 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 956 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 957 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 958 csBundle(1).uopIdx := 1.U 959 csBundle(2).lsrc(0) := src1 960 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 961 csBundle(2).ldest := dest 962 csBundle(2).uopIdx := 2.U 963 } 964 } 965 when(vlmul === VLmul.mf4) { 966 when(vsew === VSew.e16) { 967 csBundle(0).lsrc(0) := src2 968 csBundle(0).lsrc(1) := src2 969 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 970 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 971 csBundle(0).uopIdx := 0.U 972 csBundle(1).lsrc(0) := src1 973 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 974 csBundle(1).ldest := dest 975 csBundle(1).uopIdx := 1.U 976 } 977 } 978 } 979 980 is(UopSplitType.VEC_VFREDOSUM) { 981 import yunsuan.VfaluType 982 val vlmul = vlmulReg 983 val vsew = vsewReg 984 val isWiden = latchedInst.fuOpType === VfaluType.vfwredosum 985 when(vlmul === VLmul.m8) { 986 when(vsew === VSew.e64) { 987 val vlmax = 16 988 for (i <- 0 until vlmax) { 989 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 990 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 991 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 992 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 993 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 994 csBundle(i).uopIdx := i.U 995 } 996 } 997 when(vsew === VSew.e32) { 998 val vlmax = 32 999 for (i <- 0 until vlmax) { 1000 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1001 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1002 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1003 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1004 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 1005 csBundle(i).uopIdx := i.U 1006 } 1007 } 1008 when(vsew === VSew.e16) { 1009 val vlmax = 64 1010 for (i <- 0 until vlmax) { 1011 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1012 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1013 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1014 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1015 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 1016 csBundle(i).uopIdx := i.U 1017 } 1018 } 1019 } 1020 when(vlmul === VLmul.m4) { 1021 when(vsew === VSew.e64) { 1022 val vlmax = 8 1023 for (i <- 0 until vlmax) { 1024 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1025 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1026 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1027 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1028 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1029 csBundle(i).uopIdx := i.U 1030 } 1031 } 1032 when(vsew === VSew.e32) { 1033 val vlmax = 16 1034 for (i <- 0 until vlmax) { 1035 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1036 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1037 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1038 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1039 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1040 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1041 csBundle(i).uopIdx := i.U 1042 } 1043 } 1044 when(vsew === VSew.e16) { 1045 val vlmax = 32 1046 for (i <- 0 until vlmax) { 1047 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1048 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1049 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1050 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1051 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1052 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1053 csBundle(i).uopIdx := i.U 1054 } 1055 } 1056 } 1057 when(vlmul === VLmul.m2) { 1058 when(vsew === VSew.e64) { 1059 val vlmax = 4 1060 for (i <- 0 until vlmax) { 1061 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1062 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1063 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1064 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1065 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1066 csBundle(i).uopIdx := i.U 1067 } 1068 } 1069 when(vsew === VSew.e32) { 1070 val vlmax = 8 1071 for (i <- 0 until vlmax) { 1072 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1073 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1074 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1075 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1076 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1077 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1078 csBundle(i).uopIdx := i.U 1079 } 1080 } 1081 when(vsew === VSew.e16) { 1082 val vlmax = 16 1083 for (i <- 0 until vlmax) { 1084 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1085 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1086 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1087 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1088 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1089 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1090 csBundle(i).uopIdx := i.U 1091 } 1092 } 1093 } 1094 when(vlmul === VLmul.m1) { 1095 when(vsew === VSew.e64) { 1096 val vlmax = 2 1097 for (i <- 0 until vlmax) { 1098 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1099 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1100 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1101 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1102 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1103 csBundle(i).uopIdx := i.U 1104 } 1105 } 1106 when(vsew === VSew.e32) { 1107 val vlmax = 4 1108 for (i <- 0 until vlmax) { 1109 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1110 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1111 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1112 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1113 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1114 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1115 csBundle(i).uopIdx := i.U 1116 } 1117 } 1118 when(vsew === VSew.e16) { 1119 val vlmax = 8 1120 for (i <- 0 until vlmax) { 1121 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1122 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1123 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1124 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1125 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1126 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1127 csBundle(i).uopIdx := i.U 1128 } 1129 } 1130 } 1131 when(vlmul === VLmul.mf2) { 1132 when(vsew === VSew.e32) { 1133 val vlmax = 2 1134 for (i <- 0 until vlmax) { 1135 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1136 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1137 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1138 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1139 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1140 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1141 csBundle(i).uopIdx := i.U 1142 } 1143 } 1144 when(vsew === VSew.e16) { 1145 val vlmax = 4 1146 for (i <- 0 until vlmax) { 1147 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1148 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1149 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1150 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1151 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1152 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1153 csBundle(i).uopIdx := i.U 1154 } 1155 } 1156 } 1157 when(vlmul === VLmul.mf4) { 1158 when(vsew === VSew.e16) { 1159 val vlmax = 2 1160 for (i <- 0 until vlmax) { 1161 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1162 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1163 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1164 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1165 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1166 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1167 csBundle(i).uopIdx := i.U 1168 } 1169 } 1170 } 1171 } 1172 1173 is(UopSplitType.VEC_SLIDEUP) { 1174 // i to vector move 1175 csBundle(0).srcType(0) := SrcType.reg 1176 csBundle(0).srcType(1) := SrcType.imm 1177 csBundle(0).lsrc(1) := 0.U 1178 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1179 csBundle(0).fuType := FuType.i2v.U 1180 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1181 csBundle(0).vecWen := true.B 1182 // LMUL 1183 for (i <- 0 until MAX_VLMUL) 1184 for (j <- 0 to i) { 1185 val old_vd = if (j == 0) { 1186 dest + i.U 1187 } else (VECTOR_TMP_REG_LMUL + j).U 1188 val vd = if (j == i) { 1189 dest + i.U 1190 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1191 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.vp 1192 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1193 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1194 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1195 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1196 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1197 } 1198 } 1199 1200 is(UopSplitType.VEC_SLIDEDOWN) { 1201 // i to vector move 1202 csBundle(0).srcType(0) := SrcType.reg 1203 csBundle(0).srcType(1) := SrcType.imm 1204 csBundle(0).lsrc(1) := 0.U 1205 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1206 csBundle(0).fuType := FuType.i2v.U 1207 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1208 csBundle(0).vecWen := true.B 1209 // LMUL 1210 for (i <- 0 until MAX_VLMUL) 1211 for (j <- (0 to i).reverse) { 1212 when(i.U < lmul) { 1213 val old_vd = if (j == 0) { 1214 dest + lmul - 1.U - i.U 1215 } else (VECTOR_TMP_REG_LMUL + j).U 1216 val vd = if (j == i) { 1217 dest + lmul - 1.U - i.U 1218 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1219 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.vp 1220 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1221 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1222 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1223 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1224 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1225 } 1226 } 1227 } 1228 1229 is(UopSplitType.VEC_M0X) { 1230 // LMUL 1231 for (i <- 0 until MAX_VLMUL) { 1232 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1233 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1234 csBundle(i).srcType(0) := srcType0 1235 csBundle(i).srcType(1) := SrcType.vp 1236 csBundle(i).rfWen := false.B 1237 csBundle(i).fpWen := false.B 1238 csBundle(i).vecWen := true.B 1239 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1240 csBundle(i).lsrc(1) := src2 1241 // csBundle(i).lsrc(2) := dest + i.U DontCare 1242 csBundle(i).ldest := ldest 1243 csBundle(i).uopIdx := i.U 1244 } 1245 csBundle(lmul - 1.U).rfWen := true.B 1246 csBundle(lmul - 1.U).fpWen := false.B 1247 csBundle(lmul - 1.U).vecWen := false.B 1248 csBundle(lmul - 1.U).ldest := dest 1249 } 1250 1251 is(UopSplitType.VEC_MVV) { 1252 // LMUL 1253 for (i <- 0 until MAX_VLMUL) { 1254 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1255 csBundle(i * 2 + 0).srcType(0) := srcType0 1256 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1257 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1258 csBundle(i * 2 + 0).lsrc(1) := src2 1259 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1260 csBundle(i * 2 + 0).ldest := dest + i.U 1261 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1262 1263 csBundle(i * 2 + 1).srcType(0) := srcType0 1264 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1265 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1266 csBundle(i * 2 + 1).lsrc(1) := src2 1267 // csBundle(i).lsrc(2) := dest + i.U DontCare 1268 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1269 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1270 } 1271 } 1272 1273 is(UopSplitType.VEC_M0X_VFIRST) { 1274 // LMUL 1275 csBundle(0).rfWen := true.B 1276 csBundle(0).fpWen := false.B 1277 csBundle(0).vecWen := false.B 1278 csBundle(0).ldest := dest 1279 } 1280 is(UopSplitType.VEC_VWW) { 1281 for (i <- 0 until MAX_VLMUL*2) { 1282 when(i.U < lmul){ 1283 csBundle(i).srcType(2) := SrcType.DC 1284 csBundle(i).lsrc(0) := src2 + i.U 1285 csBundle(i).lsrc(1) := src2 + i.U 1286 // csBundle(i).lsrc(2) := dest + (2 * i).U 1287 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1288 csBundle(i).uopIdx := i.U 1289 } otherwise { 1290 csBundle(i).srcType(2) := SrcType.DC 1291 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1292 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1293 // csBundle(i).lsrc(2) := dest + (2 * i).U 1294 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1295 csBundle(i).uopIdx := i.U 1296 } 1297 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1298 csBundle(numOfUop-1.U).lsrc(0) := src1 1299 csBundle(numOfUop-1.U).lsrc(2) := dest 1300 csBundle(numOfUop-1.U).ldest := dest 1301 } 1302 } 1303 is(UopSplitType.VEC_RGATHER) { 1304 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1305 for (i <- 0 until len) 1306 for (j <- 0 until len) { 1307 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1308 // csBundle(i * len + j).srcType(1) := SrcType.vp 1309 // csBundle(i * len + j).srcType(2) := SrcType.vp 1310 csBundle(i * len + j).lsrc(0) := src1 + i.U 1311 csBundle(i * len + j).lsrc(1) := src2 + j.U 1312 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1313 csBundle(i * len + j).lsrc(2) := vd_old 1314 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1315 csBundle(i * len + j).ldest := vd 1316 csBundle(i * len + j).uopIdx := (i * len + j).U 1317 } 1318 } 1319 switch(vlmulReg) { 1320 is("b001".U ){ 1321 genCsBundle_VEC_RGATHER(2) 1322 } 1323 is("b010".U ){ 1324 genCsBundle_VEC_RGATHER(4) 1325 } 1326 is("b011".U ){ 1327 genCsBundle_VEC_RGATHER(8) 1328 } 1329 } 1330 } 1331 is(UopSplitType.VEC_RGATHER_VX) { 1332 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1333 for (i <- 0 until len) 1334 for (j <- 0 until len) { 1335 csBundle(i * len + j + 1).srcType(0) := SrcType.vp 1336 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1337 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1338 csBundle(i * len + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1339 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1340 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1341 csBundle(i * len + j + 1).lsrc(2) := vd_old 1342 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1343 csBundle(i * len + j + 1).ldest := vd 1344 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1345 } 1346 } 1347 // i to vector move 1348 csBundle(0).srcType(0) := SrcType.reg 1349 csBundle(0).srcType(1) := SrcType.imm 1350 csBundle(0).lsrc(1) := 0.U 1351 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1352 csBundle(0).fuType := FuType.i2v.U 1353 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1354 csBundle(0).vecWen := true.B 1355 switch(vlmulReg) { 1356 is("b000".U ){ 1357 genCsBundle_RGATHER_VX(1) 1358 } 1359 is("b001".U ){ 1360 genCsBundle_RGATHER_VX(2) 1361 } 1362 is("b010".U ){ 1363 genCsBundle_RGATHER_VX(4) 1364 } 1365 is("b011".U ){ 1366 genCsBundle_RGATHER_VX(8) 1367 } 1368 } 1369 } 1370 is(UopSplitType.VEC_RGATHEREI16) { 1371 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1372 for (i <- 0 until len) 1373 for (j <- 0 until len) { 1374 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1375 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1376 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1377 // csBundle(i * len + j).srcType(1) := SrcType.vp 1378 // csBundle(i * len + j).srcType(2) := SrcType.vp 1379 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1380 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1381 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1382 csBundle((i * len + j)*2+0).ldest := vd0 1383 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1384 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1385 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1386 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1387 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1388 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1389 csBundle((i * len + j)*2+1).ldest := vd1 1390 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1391 } 1392 } 1393 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1394 for (i <- 0 until len) 1395 for (j <- 0 until len) { 1396 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1397 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1398 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1399 // csBundle(i * len + j).srcType(1) := SrcType.vp 1400 // csBundle(i * len + j).srcType(2) := SrcType.vp 1401 csBundle(i * len + j).lsrc(0) := src1 + i.U 1402 csBundle(i * len + j).lsrc(1) := src2 + j.U 1403 csBundle(i * len + j).lsrc(2) := vd_old 1404 csBundle(i * len + j).ldest := vd 1405 csBundle(i * len + j).uopIdx := (i * len + j).U 1406 } 1407 } 1408 switch(vlmulReg) { 1409 is("b000".U ){ 1410 when(!vsewReg.orR){ 1411 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1412 } .otherwise{ 1413 genCsBundle_VEC_RGATHEREI16(1) 1414 } 1415 } 1416 is("b001".U) { 1417 when(!vsewReg.orR) { 1418 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1419 }.otherwise { 1420 genCsBundle_VEC_RGATHEREI16(2) 1421 } 1422 } 1423 is("b010".U) { 1424 when(!vsewReg.orR) { 1425 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1426 }.otherwise { 1427 genCsBundle_VEC_RGATHEREI16(4) 1428 } 1429 } 1430 is("b011".U) { 1431 genCsBundle_VEC_RGATHEREI16(8) 1432 } 1433 } 1434 } 1435 is(UopSplitType.VEC_COMPRESS) { 1436 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1437 for (i <- 0 until len){ 1438 val jlen = if (i == len-1) i+1 else i+2 1439 for (j <- 0 until jlen) { 1440 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1441 val vd = if(i==len-1) (dest + j.U) else{ 1442 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1443 } 1444 val src23Type = if (j == i+1) DontCare else SrcType.vp 1445 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1446 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1447 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1448 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1449 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1450 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1451 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1452 csBundle(i*(i+3)/2 + j).ldest := vd 1453 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1454 } 1455 } 1456 } 1457 switch(vlmulReg) { 1458 is("b001".U ){ 1459 genCsBundle_VEC_COMPRESS(2) 1460 } 1461 is("b010".U ){ 1462 genCsBundle_VEC_COMPRESS(4) 1463 } 1464 is("b011".U ){ 1465 genCsBundle_VEC_COMPRESS(8) 1466 } 1467 } 1468 } 1469 is(UopSplitType.VEC_MVNR) { 1470 for (i <- 0 until MAX_VLMUL) { 1471 csBundle(i).lsrc(0) := src1 + i.U 1472 csBundle(i).lsrc(1) := src2 + i.U 1473 csBundle(i).lsrc(2) := dest + i.U 1474 csBundle(i).ldest := dest + i.U 1475 csBundle(i).uopIdx := i.U 1476 } 1477 } 1478 is(UopSplitType.VEC_US_LDST) { 1479 /* 1480 FMV.D.X 1481 */ 1482 csBundle(0).srcType(0) := SrcType.reg 1483 csBundle(0).srcType(1) := SrcType.imm 1484 csBundle(0).lsrc(1) := 0.U 1485 csBundle(0).ldest := FP_TMP_REG_MV.U 1486 csBundle(0).fuType := FuType.i2f.U 1487 csBundle(0).rfWen := false.B 1488 csBundle(0).fpWen := true.B 1489 csBundle(0).vecWen := false.B 1490 csBundle(0).fpu.isAddSub := false.B 1491 csBundle(0).fpu.typeTagIn := FPU.D 1492 csBundle(0).fpu.typeTagOut := FPU.D 1493 csBundle(0).fpu.fromInt := true.B 1494 csBundle(0).fpu.wflags := false.B 1495 csBundle(0).fpu.fpWen := true.B 1496 csBundle(0).fpu.div := false.B 1497 csBundle(0).fpu.sqrt := false.B 1498 csBundle(0).fpu.fcvt := false.B 1499 //LMUL 1500 for (i <- 0 until MAX_VLMUL) { 1501 csBundle(i + 1).srcType(0) := SrcType.fp 1502 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1503 csBundle(i + 1).lsrc(2) := dest + i.U // old vd 1504 csBundle(i + 1).ldest := dest + i.U 1505 csBundle(i + 1).uopIdx := i.U 1506 } 1507 } 1508 is(UopSplitType.VEC_S_LDST) { 1509 /* 1510 FMV.D.X 1511 */ 1512 csBundle(0).srcType(0) := SrcType.reg 1513 csBundle(0).srcType(1) := SrcType.imm 1514 csBundle(0).lsrc(1) := 0.U 1515 csBundle(0).ldest := FP_TMP_REG_MV.U 1516 csBundle(0).fuType := FuType.i2f.U 1517 csBundle(0).rfWen := false.B 1518 csBundle(0).fpWen := true.B 1519 csBundle(0).vecWen := false.B 1520 csBundle(0).fpu.isAddSub := false.B 1521 csBundle(0).fpu.typeTagIn := FPU.D 1522 csBundle(0).fpu.typeTagOut := FPU.D 1523 csBundle(0).fpu.fromInt := true.B 1524 csBundle(0).fpu.wflags := false.B 1525 csBundle(0).fpu.fpWen := true.B 1526 csBundle(0).fpu.div := false.B 1527 csBundle(0).fpu.sqrt := false.B 1528 csBundle(0).fpu.fcvt := false.B 1529 1530 csBundle(1).srcType(0) := SrcType.reg 1531 csBundle(1).srcType(1) := SrcType.imm 1532 csBundle(1).lsrc(0) := latchedInst.lsrc(1) 1533 csBundle(1).lsrc(1) := 0.U 1534 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 1535 csBundle(1).fuType := FuType.i2f.U 1536 csBundle(1).rfWen := false.B 1537 csBundle(1).fpWen := true.B 1538 csBundle(1).vecWen := false.B 1539 csBundle(1).fpu.isAddSub := false.B 1540 csBundle(1).fpu.typeTagIn := FPU.D 1541 csBundle(1).fpu.typeTagOut := FPU.D 1542 csBundle(1).fpu.fromInt := true.B 1543 csBundle(1).fpu.wflags := false.B 1544 csBundle(1).fpu.fpWen := true.B 1545 csBundle(1).fpu.div := false.B 1546 csBundle(1).fpu.sqrt := false.B 1547 csBundle(1).fpu.fcvt := false.B 1548 1549 //LMUL 1550 for (i <- 0 until MAX_VLMUL) { 1551 csBundle(i + 2).srcType(0) := SrcType.fp 1552 csBundle(i + 2).srcType(1) := SrcType.fp 1553 csBundle(i + 2).lsrc(0) := FP_TMP_REG_MV.U 1554 csBundle(i + 2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 1555 csBundle(i + 2).lsrc(2) := dest + i.U // old vd 1556 csBundle(i + 2).ldest := dest + i.U 1557 csBundle(i + 2).uopIdx := i.U 1558 } 1559 } 1560 is(UopSplitType.VEC_I_LDST) { 1561 /* 1562 FMV.D.X 1563 */ 1564 val vlmul = vlmulReg 1565 val vsew = Cat(0.U(1.W), vsewReg) 1566 val veew = Cat(0.U(1.W), width) 1567 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 1568 val simple_lmul = MuxLookup(vlmul, 0.U(2.W), Array( 1569 "b001".U -> 1.U, 1570 "b010".U -> 2.U, 1571 "b011".U -> 3.U 1572 )) 1573 val simple_emul = MuxLookup(vemul, 0.U(2.W), Array( 1574 "b001".U -> 1.U, 1575 "b010".U -> 2.U, 1576 "b011".U -> 3.U 1577 )) 1578 csBundle(0).srcType(0) := SrcType.reg 1579 csBundle(0).srcType(1) := SrcType.imm 1580 csBundle(0).lsrc(1) := 0.U 1581 csBundle(0).ldest := FP_TMP_REG_MV.U 1582 csBundle(0).fuType := FuType.i2f.U 1583 csBundle(0).rfWen := false.B 1584 csBundle(0).fpWen := true.B 1585 csBundle(0).vecWen := false.B 1586 csBundle(0).fpu.isAddSub := false.B 1587 csBundle(0).fpu.typeTagIn := FPU.D 1588 csBundle(0).fpu.typeTagOut := FPU.D 1589 csBundle(0).fpu.fromInt := true.B 1590 csBundle(0).fpu.wflags := false.B 1591 csBundle(0).fpu.fpWen := true.B 1592 csBundle(0).fpu.div := false.B 1593 csBundle(0).fpu.sqrt := false.B 1594 csBundle(0).fpu.fcvt := false.B 1595 1596 //LMUL 1597 for (i <- 0 until MAX_INDEXED_LS_UOPNUM) { 1598 indexedLSRegOffset(i).src := Cat(simple_emul, simple_lmul, nf) 1599 val offsetVs2 = indexedLSRegOffset(i).outOffsetVs2 1600 val offsetVd = indexedLSRegOffset(i).outOffsetVd 1601 val isFirstUopInVd = indexedLSRegOffset(i).outIsFirstUopInVd 1602 csBundle(i + 1).srcType(0) := SrcType.fp 1603 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1604 csBundle(i + 1).lsrc(1) := Mux1H(UIntToOH(offsetVs2, MAX_VLMUL), (0 until MAX_VLMUL).map(j => src2 + j.U)) 1605 /** 1606 * For indexed instructions, VLSU will concatenate all the uops that write the same logic vd register and 1607 * writeback only once for all these uops. However, these uops share the same lsrc(2)/old vd and the same 1608 * ldest/vd that is equal to old vd, which leads to data dependence between the uops. Therefore there will be 1609 * deadlock for indexed instructions with emul > lmul. 1610 * 1611 * Assume N = emul/lmul. To break the deadlock, only the first uop will read old vd as lsrc(2), and the rest 1612 * N-1 uops will read temporary vector register. 1613 */ 1614 // csBundle(i + 1).lsrc(2) := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1615 csBundle(i + 1).lsrc(2) := Mux( 1616 isFirstUopInVd, 1617 Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)), 1618 VECTOR_TMP_REG_LMUL.U 1619 ) 1620 csBundle(i + 1).ldest := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1621 csBundle(i + 1).uopIdx := i.U 1622 } 1623 } 1624 } 1625 1626 //readyFromRename Counter 1627 val readyCounter = PriorityMuxDefault(outReadys.map(x => !x).zip((0 until RenameWidth).map(_.U)), RenameWidth.U) 1628 1629 // The left uops of the complex inst in ComplexDecoder can be send out this cycle 1630 val thisAllOut = uopRes <= readyCounter 1631 1632 switch(state) { 1633 is(s_idle) { 1634 when (inValid) { 1635 stateNext := s_active 1636 uopResNext := inUopInfo.numOfUop 1637 } 1638 } 1639 is(s_active) { 1640 when (thisAllOut) { 1641 when (inValid) { 1642 stateNext := s_active 1643 uopResNext := inUopInfo.numOfUop 1644 }.otherwise { 1645 stateNext := s_idle 1646 uopResNext := 0.U 1647 } 1648 }.otherwise { 1649 stateNext := s_active 1650 uopResNext := uopRes - readyCounter 1651 } 1652 } 1653 } 1654 1655 state := Mux(io.redirect, s_idle, stateNext) 1656 uopRes := Mux(io.redirect, 0.U, uopResNext) 1657 1658 val complexNum = Mux(uopRes > readyCounter, readyCounter, uopRes) 1659 1660 for(i <- 0 until RenameWidth) { 1661 outValids(i) := complexNum > i.U 1662 outDecodedInsts(i) := Mux((i.U + numOfUop - uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1663 } 1664 1665 outComplexNum := Mux(state === s_active, complexNum, 0.U) 1666 inReady := state === s_idle || state === s_active && thisAllOut 1667 1668// val validSimple = Wire(Vec(DecodeWidth, Bool())) 1669// validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1670// val notInf = Wire(Vec(DecodeWidth, Bool())) 1671// notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1672// notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 1673// val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1674// notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1675// 1676// complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1677// Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1678// 0.U) 1679// validToRename.zipWithIndex.foreach{ 1680// case(dst, i) => 1681// val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 1682// dst := MuxCase(false.B, Seq( 1683// (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 1684// (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1685// ).toSeq) 1686// } 1687// 1688// readyToIBuf.zipWithIndex.foreach { 1689// case (dst, i) => 1690// val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 1691// dst := MuxCase(true.B, Seq( 1692// (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 1693// (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 1694// ).toSeq) 1695// } 1696// 1697// io.deq.decodedInsts := decodedInsts 1698// io.deq.complexNum := complexNum 1699// io.deq.validToRename := validToRename 1700// io.deq.readyToIBuf := readyToIBuf 1701} 1702