LQ: fix select oldest inst & remove bank conf. block to avoid deadlock (#2100)

* LoadQueueReplay: fix worst case, all oldest instructions are allocated to the same bank,
and the number of instruct

LQ: fix select oldest inst & remove bank conf. block to avoid deadlock (#2100)

* LoadQueueReplay: fix worst case, all oldest instructions are allocated to the same bank,
and the number of instructions is greater than the number of stages in load unit.
* Remove bank conflict block
* Increase priority for data replay

The deadlock scenario is as follows:

The LoadQueueReplay entry will not be released immediately after the instruction
is replayed from LoadQueueReplay. For example, after instruction a is replayed from
LoadQueueReplay, entry 1 is still valid. If instruction a still needs to be replayed,
Entry 1 will be updated again, otherwise entry 1 can be released.

If only the time of the first enqueue is used to select replay instructions (age matrix),
when there are too many instructions (in LoadQueueReplay) to be replay, some
instructions may not be selected.

Using the pointer ldWbPtr of the oldest instruction, when the saved lqIdx of the
instruction is equal to ldWbPtr and can be replayed, LoadQueueReplay will give
priority to the instruction instead of using the selection result of the age matrix.
To select older instructions, LoadQueueReplay will calculate pointers such as
ldWbPtr, ldWbPtr+1, ldWbPtr+2, ldWbPtr+3..., and if the lqIdx of the instruction
is in these results, it will be selected first.

When the pointer is compared, there will be an n-bit long mask, and LoadQueueReplay
will be from 0 to n-1. When i th bit is valid, select i th instruction.

The stride of the pointer comparison is larger than the number of pipeline stages
of the load unit, and the selected instruction still needs to be replayed after the
first replay (for example, the data is not ready). Worse, in the bit of the mask
generated by pointer comparison, the instructions (lqIdx is ldWbPtr+1, ldWbPtr+2, ...)
after the oldest instruction (lqIdx is equal to ldWbPtr) are in the lower bit and the
oldest instruction is in the higher bit. It cannot select the oldest instruction.

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lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitSt

lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict when compare SSID

* fix store data wakeup logic

Co-authored-by: Lyn <[email protected]>

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Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu

# Conflicts:
# .gitmodules
# build.sc
# src/main/scala/top/Configs.scala
# src/main/scala/xiangshan/Bundle.scala
# src/

Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu

# Conflicts:
# .gitmodules
# build.sc
# src/main/scala/top/Configs.scala
# src/main/scala/xiangshan/Bundle.scala
# src/main/scala/xiangshan/Parameters.scala
# src/main/scala/xiangshan/XSCore.scala
# src/main/scala/xiangshan/backend/CtrlBlock.scala
# src/main/scala/xiangshan/backend/MemBlock.scala
# src/main/scala/xiangshan/backend/Scheduler.scala
# src/main/scala/xiangshan/backend/issue/ReservationStation.scala
# src/main/scala/xiangshan/backend/issue/StatusArray.scala
# src/main/scala/xiangshan/backend/rob/Rob.scala
# src/main/scala/xiangshan/mem/MemCommon.scala
# src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
# src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
# src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
# src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
# src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

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lsu, uncache buffer: fix uncache buffer writeback loadOut is incorrectly held (#2087)

* fix uncache buffer writeback fsm

* fix uncache buffer writeback fsm

* fix uncache buffer writeback contr

lsu, uncache buffer: fix uncache buffer writeback loadOut is incorrectly held (#2087)

* fix uncache buffer writeback fsm

* fix uncache buffer writeback fsm

* fix uncache buffer writeback control

---------

Co-authored-by: Lyn <[email protected]>

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lsu: split lq for larger ooo load window (#2077)

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay qu

lsu: split lq for larger ooo load window (#2077)

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay queue
* load rar queue
* load raw queue
* uncache buffer

It will provide larger ooo load window.

NOTE: IPC loss in this commit is caused by MDP problems, for previous MDP
does not fit new LSU architecture.
MDP update is not included in this commit, IPC loss will be fixed by MDP update later.

---------

Co-authored-by: Lyn <[email protected]>

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Merge remote-tracking branch 'upstream/master' into new-backend

backend: merge v2backend into backend

LoadMissTable: add it and use constant control (#1969)

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the const

LoadMissTable: add it and use constant control (#1969)

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the constant control logic

* databases: add constant control

* constantin: afix some bug

* constantin: fix txt

* fixbug: constant control in double core

* constantin: postfix changed in `verilator.mk`

* instDB: add robIdx and some TIME signals

* loadMissDB-copt: rm `resp.bits.firstHit` add `s2_first_hit`

* difftest: update

* yml: update the git workflow

* submodules: fix the binding commit-id of personal fork rep

* fix: github workflow add NOOP_HOME

because in constantin.scala use the absolute path of workdir by environment variable `NOOP_HOME`

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backend: add load inst support

Fix replay logic in unified load queue (#1966)

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use c

Fix replay logic in unified load queue (#1966)

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use counter to delay)
* if dcache's mshr gets refill data, wake up lq's missed load
* uncache load will writeback to ldu using ldout_0
* ldout_1 is no longer used

* lq, ldu: add forward port

* forward D and mshr in load S1, get result in S2
* remove useless code logic in loadQueueData

* misc: revert monitor

* lq: change replay cycle

* lq: change replay cycle
* change cycle to 11 36 10 10

* Revert "lq: change replay cycle"

This reverts commit 3ca74b63eaeef7792016cd270b77f8a14f588981.
And change replay cycles

* lq: change replay cycle according to dramsim

* change Reselectlen to 7
* change replay cycle to (11, 18, 127, 17) to fit refill delay (14, 36,
188)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 32, 51)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 126, 95)

* lq: fix replay ptr update logic

* fix priority of updating ptr
* revert block_cycles_cache

* lq: change tlb replay cycle

* change tlbReplayDelayCycleCtrl to (15, 0, 126, 0)

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v2backend: huge tmp commit

lsdb: add some information of ls instructions by chiselDB (#1900)

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL

lsdb: add some information of ls instructions by chiselDB (#1900)

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.

* ROB: add inst db drop

globalID signal output is still duplicated

* TLB: TLB will carry mem idx when req and resp

* InstDB: update the TLBFirstIssue

* InstDB: the first version is complete

* InstDB: update decode logic

* InstDB: update ctrlBlock writeback

* Merge: fix bug

* merge: fix compile bug

* code rule: rename debug signals and add db's FPGA signal control

* code rule: update db's FPGA signal control

* ldu: fix isFirstIssue flag for ldflow from rs

* ldu: isFirstIssue flag for hw pf is always false

---------

Co-authored-by: good-circle <[email protected]>
Co-authored-by: William Wang <[email protected]>

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chore: add l1 pf fuzzer

lq: fix vaddr raddr

chore: fix more l1 pf merge conflicts

ldu: support prefetch to l1 dcache

dcache: setup way predictor framework (#1857)

This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache da

dcache: setup way predictor framework (#1857)

This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache data SRAMs
have been reorganized for that.

The dummy predictor is disabled by default.

Besides, dcache bank conflict check has been optimized. It may cause timing problems,
to be fixed in the future.

* ideal wpu

* BankedDataArray: change architecture to reduce bank_conflict

* BankedDataArray: add db analysis

* Merge: the rest

* BankedDataArray: change the logic of rrl_bank_conflict, but let the number of rw_bank_conflict up

* Load Logic: changed to be as expected

reading data will be delayed by one cycle to make selection
writing data will be also delayed by one cycle to do write operation

* fix: ecc check error

* update the gitignore

* WPU: add regular wpu and change the replay mechanism

* WPU: fix refill fail bug, but a new addiw fail bug appears

* WPU: temporarily turn off to PR

* WPU: tfix all bug

* loadqueue: fix the initialization of replayCarry

* bankeddataarray: fix the bug

* DCacheWrapper: fix bug

* ready-to-run: correct the version

* WayPredictor: comments clean

* BankedDataArray: fix ecc_bank bug

* Parameter: set the enable signal of wpu

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lq: Remove LQ data (#1862)

This PR remove data in lq.

All cache miss load instructions will be replayed by lq, and the forward path to the D channel
and mshr is added to the pipeline.
Special t

lq: Remove LQ data (#1862)

This PR remove data in lq.

All cache miss load instructions will be replayed by lq, and the forward path to the D channel
and mshr is added to the pipeline.
Special treatment is made for uncache load. The data is no longer stored in the datamodule
but stored in a separate register. ldout is only used as uncache writeback, and only ldout0
will be used. Adjust the priority so that the replayed instruction has the highest priority in S0.

Future work:
1. fix `milc` perf loss
2. remove data from MSHRs

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use counter to delay)
* if dcache's mshr gets refill data, wake up lq's missed load
* uncache load will writeback to ldu using ldout_0
* ldout_1 is no longer used

* lq, ldu: add forward port

* forward D and mshr in load S1, get result in S2
* remove useless code logic in loadQueueData

* misc: revert monitor

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

ldu: add st-ld violation re-execute (#1849)

* lsu: add st-ld violation re-execute

* misc: update vio check comments in LQ

Co-authored-by: Lyn <[email protected]>
Co-authored-by: Will

ldu: add st-ld violation re-execute (#1849)

* lsu: add st-ld violation re-execute

* misc: update vio check comments in LQ

Co-authored-by: Lyn <[email protected]>
Co-authored-by: William Wang <[email protected]>

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Uncache: optimize write operation (#1844)

This commit adds an uncache write buffer to accelerate uncache write

For uncacheable address range, now we use atomic bit in PMA to indicate
uncache wri

Uncache: optimize write operation (#1844)

This commit adds an uncache write buffer to accelerate uncache write

For uncacheable address range, now we use atomic bit in PMA to indicate
uncache write in this range should not use uncache write buffer.

Note that XiangShan does not support atomic insts in uncacheable address range.

* uncache: optimize write operation

* pma: add atomic config

* uncache: assign hartId

* remove some pma atomic

* extend peripheral id width

Co-authored-by: Lyn <[email protected]>

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Replay all load instructions from LQ (#1838)

This intermediate architecture replays all load instructions from LQ.
An independent load replay queue will be added later.

Performance loss caused b

Replay all load instructions from LQ (#1838)

This intermediate architecture replays all load instructions from LQ.
An independent load replay queue will be added later.

Performance loss caused by changing of load replay sequences will be
analyzed in the future.

* memblock: load queue based replay

* replay load from load queue rather than RS
* use counters to delay replay logic

* memblock: refactor priority

* lsq-replay has higher priority than try pointchasing

* RS: remove load store rs's feedback port

* ld-replay: a new path for fast replay

* when fast replay needed, wire it to loadqueue and it will be selected
this cycle and replay to load pipline s0 in next cycle

* memblock: refactor load S0

* move all the select logic from lsq to load S0
* split a tlbReplayDelayCycleCtrl out of loadqueue to speed up
generating emu

* loadqueue: parameterize replay

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Merge pull request #1831 from OpenXiangShan/nanhu-lsu-timing-to-master

Rebase nanhu lsu timing opt to master

ldu: select data in load_s3 (#1743)

rdataVec (i.e. sram read result merge forward result) is still
generated in load_s2. It will be write to load queue in load_s2

lq: update paddr in lq in load_s1 and load_s2 (#1707)

Now we use 2 cycles to update paddr in lq. In this way,
paddr in lq is still valid in load_s3