1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend._ 26import xiangshan.backend.decode.ImmUnion 27import xiangshan.backend.decode.isa._ 28 29trait HasRedirectOut { this: XSModule => 30 val redirectOutValid = IO(Output(Bool())) 31 val redirectOut = IO(Output(new Redirect)) 32} 33 34class JumpDataModule(implicit p: Parameters) extends XSModule { 35 val io = IO(new Bundle() { 36 val src = Input(UInt(XLEN.W)) 37 val pc = Input(UInt(XLEN.W)) // sign-ext to XLEN 38 val immMin = Input(UInt(ImmUnion.maxLen.W)) 39 val func = Input(FuOpType()) 40 val isRVC = Input(Bool()) 41 val result, target = Output(UInt(XLEN.W)) 42 val isAuipc = Output(Bool()) 43 }) 44 val (src1, pc, immMin, func, isRVC) = (io.src, io.pc, io.immMin, io.func, io.isRVC) 45 46 val isJalr = JumpOpType.jumpOpisJalr(func) 47 val isAuipc = JumpOpType.jumpOpisAuipc(func) 48 val offset = SignExt(ParallelMux(Seq( 49 isJalr -> ImmUnion.I.toImm32(immMin), 50 isAuipc -> ImmUnion.U.toImm32(immMin), 51 !(isJalr || isAuipc) -> ImmUnion.J.toImm32(immMin) 52 )), XLEN) 53 54 val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 55 val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 56 57 // RISC-V spec for JALR: 58 // The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, 59 // then setting the least-significant bit of the result to zero. 60 io.target := Cat(target(XLEN - 1, 1), false.B) 61 io.result := Mux(JumpOpType.jumpOpisAuipc(func), target, snpc) 62 io.isAuipc := isAuipc 63} 64 65//class Jump(implicit p: Parameters) extends FUWithRedirect { 66// 67// val (src1, jalr_target, pc, immMin, func, uop) = ( 68// io.in.bits.src(0), 69// io.in.bits.src(1)(VAddrBits - 1, 0), 70// SignExt(io.in.bits.uop.cf.pc, XLEN), 71// io.in.bits.uop.ctrl.imm, 72// io.in.bits.uop.ctrl.fuOpType, 73// io.in.bits.uop 74// ) 75// 76// val redirectHit = uop.robIdx.needFlush(io.redirectIn) 77// val valid = io.in.valid 78// val isRVC = uop.cf.pd.isRVC 79// 80// val jumpDataModule = Module(new JumpDataModule) 81// jumpDataModule.io.src := src1 82// jumpDataModule.io.pc := pc 83// jumpDataModule.io.immMin := immMin 84// jumpDataModule.io.func := func 85// jumpDataModule.io.isRVC := isRVC 86// 87// redirectOutValid := valid && !jumpDataModule.io.isAuipc 88// redirectOut := DontCare 89// redirectOut.level := RedirectLevel.flushAfter 90// redirectOut.robIdx := uop.robIdx 91// redirectOut.ftqIdx := uop.cf.ftqPtr 92// redirectOut.ftqOffset := uop.cf.ftqOffset 93// redirectOut.cfiUpdate.predTaken := true.B 94// redirectOut.cfiUpdate.taken := true.B 95// redirectOut.cfiUpdate.target := jumpDataModule.io.target 96// redirectOut.cfiUpdate.isMisPred := jumpDataModule.io.target(VAddrBits - 1, 0) =/= jalr_target || !uop.cf.pred_taken 97// redirectOut.debug_runahead_checkpoint_id := uop.debugInfo.runahead_checkpoint_id 98// 99// io.in.ready := io.out.ready 100// io.out.valid := valid 101// io.out.bits.uop <> io.in.bits.uop 102// io.out.bits.data := jumpDataModule.io.result 103// 104// // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 105// XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d)\n", 106// io.in.valid, 107// io.in.ready, 108// io.out.valid, 109// io.out.ready, 110// io.redirectIn.valid, 111// io.redirectIn.bits.level, 112// redirectHit 113// ) 114//} 115