1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend._ 26import xiangshan.backend.decode.ImmUnion 27import xiangshan.backend.decode.isa._ 28 29trait HasRedirectOut { this: XSModule => 30 val redirectOutValid = IO(Output(Bool())) 31 val redirectOut = IO(Output(new Redirect)) 32} 33 34class JumpDataModule(implicit p: Parameters) extends XSModule { 35 val io = IO(new Bundle() { 36 val src = Input(UInt(XLEN.W)) 37 val pc = Input(UInt(XLEN.W)) // sign-ext to XLEN 38 val imm = Input(UInt(33.W)) // imm-U need 32 bits, highest bit is sign bit 39 val nextPcOffset = Input(UInt((log2Up(PredictWidth) + 1).W)) 40 val func = Input(FuOpType()) 41 val isRVC = Input(Bool()) 42 val result, target = Output(UInt(XLEN.W)) 43 val isAuipc = Output(Bool()) 44 }) 45 val (src1, pc, imm, func, isRVC) = (io.src, io.pc, io.imm, io.func, io.isRVC) 46 47 val isJalr = JumpOpType.jumpOpisJalr(func) 48 val isAuipc = JumpOpType.jumpOpisAuipc(func) 49 val offset = SignExt(imm, XLEN) 50 51 val snpc = pc + (io.nextPcOffset << instOffsetBits).asUInt 52 val target = Mux(JumpOpType.jumpOpisJalr(func), src1 + offset, pc + offset) // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 53 54 // RISC-V spec for JALR: 55 // The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, 56 // then setting the least-significant bit of the result to zero. 57 io.target := Cat(target(XLEN - 1, 1), false.B) 58 io.result := Mux(JumpOpType.jumpOpisAuipc(func), target, snpc) 59 io.isAuipc := isAuipc 60} 61