timing(jumpUnit): fix target timing

area(backend): only use startAddr in pcMem

jump: separate src and pc

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

backend,Core: remove dead code and comments

v2backend: huge tmp commit

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

jump: set the LSB of the target to zero (#1342)

According to RISC-V spec, for the JALR instruction, its target address
is obtained by adding the sign-extended 12-bit I-immediate to the
register rs

jump: set the LSB of the target to zero (#1342)

According to RISC-V spec, for the JALR instruction, its target address
is obtained by adding the sign-extended 12-bit I-immediate to the
register rs1, then setting the least-significant bit of the result
to zero.

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core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

Add runahead debug signals (#1082)

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does no

Add runahead debug signals (#1082)

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does not support instruction fusion, disable that
in XiangShan if runahead is needed

* runahead: bump version

* difftest: bump version to support runahead

* chore: bump huancun to make ci happy

* chore: fix wrong submodule url

* difftest: bump version

BREAKING CHANGE: nemu update_config api has changed

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misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

backend: add ExuBlock to wrap execution units and RS (#903)

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
--> --> Scheduler --> RS

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

bundle: use Vec for src in ExuInput (#805)

This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt).
Should be easier for RS.

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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jump: use lower 39bits of target pc to generate isMisPred (#706)

perf: Add perf counters for predictors

fpu: wrap data part in a data module

Alu, Jump, Mul: wrap data in a dataModule

Jump: use parallel mux to generate offset

Jump: sign ext pc

jump: set isMisPred when jump does not pred_taken

Merge remote-tracking branch 'origin/opt-exception' into ftq