xref: /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala (revision 37225120844659e65ee2b406d16ab7853adce304)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19
20import chipsalliance.rocketchip.config.Parameters
21import chisel3._
22import chisel3.util._
23import xiangshan._
24import utils._
25import xiangshan.backend.rob.RobPtr
26import xiangshan.cache._
27import xiangshan.backend.fu.FenceToSbuffer
28
29object genWmask {
30  def apply(addr: UInt, sizeEncode: UInt): UInt = {
31    (LookupTree(sizeEncode, List(
32      "b00".U -> 0x1.U, //0001 << addr(2:0)
33      "b01".U -> 0x3.U, //0011
34      "b10".U -> 0xf.U, //1111
35      "b11".U -> 0xff.U //11111111
36    )) << addr(2, 0)).asUInt()
37  }
38}
39
40object genWdata {
41  def apply(data: UInt, sizeEncode: UInt): UInt = {
42    LookupTree(sizeEncode, List(
43      "b00".U -> Fill(8, data(7, 0)),
44      "b01".U -> Fill(4, data(15, 0)),
45      "b10".U -> Fill(2, data(31, 0)),
46      "b11".U -> data
47    ))
48  }
49}
50
51class LsPipelineBundle(implicit p: Parameters) extends XSBundleWithMicroOp {
52  val vaddr = UInt(VAddrBits.W)
53  val paddr = UInt(PAddrBits.W)
54  // val func = UInt(6.W)
55  val mask = UInt(8.W)
56  val data = UInt((XLEN+1).W)
57  val wlineflag = Bool() // store write the whole cache line
58
59  val miss = Bool()
60  val tlbMiss = Bool()
61  val ptwBack = Bool()
62  val mmio = Bool()
63  val atomic = Bool()
64  val rsIdx = UInt(log2Up(IssQueSize).W)
65
66  val forwardMask = Vec(8, Bool())
67  val forwardData = Vec(8, UInt(8.W))
68
69  //softprefetch
70  val isSoftPrefetch = Bool()
71
72  // For debug usage
73  val isFirstIssue = Bool()
74
75  // For load replay
76  val isLoadReplay = Bool()
77}
78
79class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle {
80  // queue entry data, except flag bits, will be updated if writeQueue is true,
81  // valid bit in LqWriteBundle will be ignored
82  val lq_data_wen_dup = Vec(6, Bool()) // dirty reg dup
83
84  def fromLsPipelineBundle(input: LsPipelineBundle) = {
85    vaddr := input.vaddr
86    paddr := input.paddr
87    mask := input.mask
88    data := input.data
89    uop := input.uop
90    wlineflag := input.wlineflag
91    miss := input.miss
92    tlbMiss := input.tlbMiss
93    ptwBack := input.ptwBack
94    mmio := input.mmio
95    atomic := input.atomic
96    rsIdx := input.rsIdx
97    forwardMask := input.forwardMask
98    forwardData := input.forwardData
99    isSoftPrefetch := input.isSoftPrefetch
100    isFirstIssue := input.isFirstIssue
101    isLoadReplay := input.isLoadReplay
102
103    lq_data_wen_dup := DontCare
104  }
105}
106
107class LoadForwardQueryIO(implicit p: Parameters) extends XSBundleWithMicroOp {
108  val vaddr = Output(UInt(VAddrBits.W))
109  val paddr = Output(UInt(PAddrBits.W))
110  val mask = Output(UInt(8.W))
111  override val uop = Output(new MicroOp) // for replay
112  val pc = Output(UInt(VAddrBits.W)) //for debug
113  val valid = Output(Bool())
114
115  val forwardMaskFast = Input(Vec(8, Bool())) // resp to load_s1
116  val forwardMask = Input(Vec(8, Bool())) // resp to load_s2
117  val forwardData = Input(Vec(8, UInt(8.W))) // resp to load_s2
118
119  // val lqIdx = Output(UInt(LoadQueueIdxWidth.W))
120  val sqIdx = Output(new SqPtr)
121
122  // dataInvalid suggests store to load forward found forward should happen,
123  // but data is not available for now. If dataInvalid, load inst should
124  // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid
125  val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now
126
127  // matchInvalid suggests in store to load forward logic, paddr cam result does
128  // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception
129  // should be raised to flush SQ and committed sbuffer.
130  val matchInvalid = Input(Bool()) // resp to load_s2
131}
132
133// LoadForwardQueryIO used in load pipeline
134//
135// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO:
136// PipeIO use predecoded sqIdxMask for better forward timing
137class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO {
138  // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons
139  // sqIdxMask is calcuated in earlier stage for better timing
140  val sqIdxMask = Output(UInt(StoreQueueSize.W))
141
142  // dataInvalid: addr match, but data is not valid for now
143  val dataInvalidFast = Input(Bool()) // resp to load_s1
144  // val dataInvalid = Input(Bool()) // resp to load_s2
145  val dataInvalidSqIdx = Input(UInt(log2Up(StoreQueueSize).W)) // resp to load_s2, sqIdx value
146}
147
148// Query load queue for ld-ld violation
149//
150// Req should be send in load_s1
151// Resp will be generated 1 cycle later
152//
153// Note that query req may be !ready, as dcache is releasing a block
154// If it happens, a replay from rs is needed.
155
156class LoadViolationQueryReq(implicit p: Parameters) extends XSBundleWithMicroOp { // provide lqIdx
157  val paddr = UInt(PAddrBits.W)
158}
159
160class LoadViolationQueryResp(implicit p: Parameters) extends XSBundle {
161  val have_violation = Bool()
162}
163
164class LoadViolationQueryIO(implicit p: Parameters) extends XSBundle {
165  val req = Decoupled(new LoadViolationQueryReq)
166  val resp = Flipped(Valid(new LoadViolationQueryResp))
167}
168
169// Store byte valid mask write bundle
170//
171// Store byte valid mask write to SQ takes 2 cycles
172class StoreMaskBundle(implicit p: Parameters) extends XSBundle {
173  val sqIdx = new SqPtr
174  val mask = UInt(8.W)
175}
176
177class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle {
178  val bankedDcacheData = Vec(DCacheBanks, UInt(64.W))
179  val bank_oh = UInt(DCacheBanks.W)
180  val forwardMask = Vec(8, Bool())
181  val forwardData = Vec(8, UInt(8.W))
182  val uop = new MicroOp // for data selection, only fwen and fuOpType are used
183  val addrOffset = UInt(3.W) // for data selection
184
185  // val dcacheData = UInt(64.W)
186  def dcacheData(): UInt = {
187    Mux1H(bank_oh, bankedDcacheData)
188  }
189
190  def mergedData(): UInt = {
191    val rdataVec = VecInit((0 until XLEN / 8).map(j =>
192      Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j))
193    ))
194    rdataVec.asUInt
195  }
196}
197
198// Load writeback data from load queue (refill)
199class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle {
200  val lqData = UInt(64.W) // load queue has merged data
201  val uop = new MicroOp // for data selection, only fwen and fuOpType are used
202  val addrOffset = UInt(3.W) // for data selection
203
204  def mergedData(): UInt = {
205    lqData
206  }
207}
208
209// Bundle for load / store wait waking up
210class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle {
211  val staIssue = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
212  val stdIssue = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
213}
214
215object AddPipelineReg {
216  class PipelineRegModule[T <: Data](gen: T) extends Module {
217    val io = IO(new Bundle() {
218      val in = Flipped(DecoupledIO(gen.cloneType))
219      val out = DecoupledIO(gen.cloneType)
220      val isFlush = Input(Bool())
221    })
222
223    val valid = RegInit(false.B)
224    valid.suggestName("pipeline_reg_valid")
225    when (io.out.fire()) { valid := false.B }
226    when (io.in.fire()) { valid := true.B }
227    when (io.isFlush) { valid := false.B }
228
229    io.in.ready := !valid || io.out.ready
230    io.out.bits := RegEnable(io.in.bits, io.in.fire())
231    io.out.valid := valid //&& !isFlush
232  }
233
234  def apply[T <: Data]
235  (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool,
236   moduleName: Option[String] = None
237  ){
238    val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType))
239    if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get)
240    pipelineReg.io.in <> left
241    right <> pipelineReg.io.out
242    pipelineReg.io.isFlush := isFlush
243  }
244}
245