1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import fudian.utils.SignExt 6import xiangshan.SelImm 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.backend.datapath.DataConfig._ 9 10class ImmExtractorIO(dataBits: Int) extends Bundle { 11 val in = Input(new Bundle { 12 val imm = UInt(64.W) 13 val immType = SelImm() 14 }) 15 val out = Output(new Bundle { 16 val imm = UInt(dataBits.W) 17 }) 18} 19 20class ImmExtractor(dataBits: Int, immTypeSet: Set[BigInt]) extends Module { 21 val io = IO(new ImmExtractorIO(dataBits)) 22 23 val extractMap = Map( 24 SelImm.IMM_I.litValue -> SignExt(ImmUnion.I.toImm32(io.in.imm), IntData().dataWidth), 25 SelImm.IMM_S.litValue -> SignExt(ImmUnion.S.toImm32(io.in.imm), IntData().dataWidth), 26 SelImm.IMM_SB.litValue -> SignExt(ImmUnion.B.toImm32(io.in.imm), IntData().dataWidth), 27 SelImm.IMM_U.litValue -> SignExt(ImmUnion.U.toImm32(io.in.imm), IntData().dataWidth), 28 SelImm.IMM_UJ.litValue -> SignExt(ImmUnion.J.toImm32(io.in.imm), IntData().dataWidth), 29 SelImm.IMM_Z.litValue -> SignExt(ImmUnion.Z.toImm32(io.in.imm), IntData().dataWidth), 30 SelImm.IMM_B6.litValue -> SignExt(ImmUnion.B6.toImm32(io.in.imm),IntData().dataWidth), 31 ) 32 33 val usedMap: Map[BigInt, UInt] = extractMap.filterKeys(x => immTypeSet.contains(x)) 34 println(usedMap) 35 36 io.out.imm := MuxLookup(io.in.immType, 0.U, usedMap.map { case (k, v) => (k.U, v) }.toSeq ) 37} 38 39object ImmExtractor { 40 def apply(imm: UInt, immType: UInt, dataBits: Int, immTypeSet: Set[BigInt]): UInt = { 41 val mod = Module(new ImmExtractor(dataBits, immTypeSet)) 42 mod.io.in.imm := imm 43 mod.io.in.immType := immType 44 mod.io.out.imm 45 } 46} 47