1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableFauFTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 val ftb = Module(new FTB()(p)) 101 val ubtb =Module(new FauFTB()(p)) 102 // val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 val preds = Seq(ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 ubtb.io.in.bits.resp_in(0) := resp_in 115 tage.io.in.bits.resp_in(0) := ubtb.io.out 116 ftb.io.in.bits.resp_in(0) := tage.io.out 117 ittage.io.in.bits.resp_in(0) := ftb.io.out 118 ras.io.in.bits.resp_in(0) := ittage.io.out 119 120 (preds, ras.io.out) 121 }), 122 IBufSize: Int = 48, 123 DecodeWidth: Int = 6, 124 RenameWidth: Int = 6, 125 CommitWidth: Int = 6, 126 FtqSize: Int = 64, 127 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 128 IssQueSize: Int = 16, 129 NRPhyRegs: Int = 192, 130 LoadQueueSize: Int = 80, 131 LoadQueueNWriteBanks: Int = 8, 132 StoreQueueSize: Int = 64, 133 StoreQueueNWriteBanks: Int = 8, 134 RobSize: Int = 256, 135 dpParams: DispatchParameters = DispatchParameters( 136 IntDqSize = 16, 137 FpDqSize = 16, 138 LsDqSize = 16, 139 IntDqDeqWidth = 4, 140 FpDqDeqWidth = 4, 141 LsDqDeqWidth = 4 142 ), 143 exuParameters: ExuParameters = ExuParameters( 144 JmpCnt = 1, 145 AluCnt = 4, 146 MulCnt = 0, 147 MduCnt = 2, 148 FmacCnt = 4, 149 FmiscCnt = 2, 150 FmiscDivSqrtCnt = 0, 151 LduCnt = 2, 152 StuCnt = 2 153 ), 154 LoadPipelineWidth: Int = 2, 155 StorePipelineWidth: Int = 2, 156 StoreBufferSize: Int = 16, 157 StoreBufferThreshold: Int = 7, 158 EnsbufferWidth: Int = 2, 159 UncacheBufferSize: Int = 4, 160 EnableLoadToLoadForward: Boolean = true, 161 EnableFastForward: Boolean = false, 162 EnableLdVioCheckAfterReset: Boolean = true, 163 EnableSoftPrefetchAfterReset: Boolean = true, 164 EnableCacheErrorAfterReset: Boolean = true, 165 EnableAccurateLoadError: Boolean = true, 166 EnableUncacheWriteOutstanding: Boolean = true, 167 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 168 ReSelectLen: Int = 6, 169 itlbParameters: TLBParameters = TLBParameters( 170 name = "itlb", 171 fetchi = true, 172 useDmode = false, 173 normalNWays = 32, 174 normalReplacer = Some("plru"), 175 superNWays = 4, 176 superReplacer = Some("plru") 177 ), 178 ldtlbParameters: TLBParameters = TLBParameters( 179 name = "ldtlb", 180 normalNSets = 64, 181 normalNWays = 1, 182 normalAssociative = "sa", 183 normalReplacer = Some("setplru"), 184 superNWays = 16, 185 normalAsVictim = true, 186 outReplace = false, 187 partialStaticPMP = true, 188 outsideRecvFlush = true, 189 saveLevel = true 190 ), 191 sttlbParameters: TLBParameters = TLBParameters( 192 name = "sttlb", 193 normalNSets = 64, 194 normalNWays = 1, 195 normalAssociative = "sa", 196 normalReplacer = Some("setplru"), 197 superNWays = 16, 198 normalAsVictim = true, 199 outReplace = false, 200 partialStaticPMP = true, 201 outsideRecvFlush = true, 202 saveLevel = true 203 ), 204 refillBothTlb: Boolean = false, 205 btlbParameters: TLBParameters = TLBParameters( 206 name = "btlb", 207 normalNSets = 1, 208 normalNWays = 64, 209 superNWays = 4, 210 ), 211 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 212 NumPerfCounters: Int = 16, 213 icacheParameters: ICacheParameters = ICacheParameters( 214 tagECC = Some("parity"), 215 dataECC = Some("parity"), 216 replacer = Some("setplru"), 217 nMissEntries = 2, 218 nProbeEntries = 2, 219 nPrefetchEntries = 2, 220 hasPrefetch = true, 221 ), 222 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 223 tagECC = Some("secded"), 224 dataECC = Some("secded"), 225 replacer = Some("setplru"), 226 nMissEntries = 16, 227 nProbeEntries = 8, 228 nReleaseEntries = 18 229 )), 230 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 231 name = "l2", 232 level = 2, 233 ways = 8, 234 sets = 1024, // default 512KB L2 235 prefetch = Some(huancun.prefetch.BOPParameters()) 236 )), 237 L2NBanks: Int = 1, 238 usePTWRepeater: Boolean = false, 239 softPTW: Boolean = false // dpi-c debug only 240){ 241 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 242 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 243 244 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 245 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 246 247 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 248 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 249 250 val fpExuConfigs = 251 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 252 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 253 254 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 255} 256 257case object DebugOptionsKey extends Field[DebugOptions] 258 259case class DebugOptions 260( 261 FPGAPlatform: Boolean = false, 262 EnableDifftest: Boolean = false, 263 AlwaysBasicDiff: Boolean = true, 264 EnableDebug: Boolean = false, 265 EnablePerfDebug: Boolean = true, 266 UseDRAMSim: Boolean = false, 267 EnableTopDown: Boolean = false 268) 269 270trait HasXSParameter { 271 272 implicit val p: Parameters 273 274 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 275 276 val coreParams = p(XSCoreParamsKey) 277 val env = p(DebugOptionsKey) 278 279 val XLEN = coreParams.XLEN 280 val minFLen = 32 281 val fLen = 64 282 def xLen = XLEN 283 284 val HasMExtension = coreParams.HasMExtension 285 val HasCExtension = coreParams.HasCExtension 286 val HasDiv = coreParams.HasDiv 287 val HasIcache = coreParams.HasICache 288 val HasDcache = coreParams.HasDCache 289 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 290 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 291 val AsidLength = coreParams.AsidLength 292 val ReSelectLen = coreParams.ReSelectLen 293 val AddrBytes = AddrBits / 8 // unused 294 val DataBits = XLEN 295 val DataBytes = DataBits / 8 296 val HasFPU = coreParams.HasFPU 297 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 298 val FetchWidth = coreParams.FetchWidth 299 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 300 val EnableBPU = coreParams.EnableBPU 301 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 302 val EnableRAS = coreParams.EnableRAS 303 val EnableLB = coreParams.EnableLB 304 val EnableLoop = coreParams.EnableLoop 305 val EnableSC = coreParams.EnableSC 306 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 307 val HistoryLength = coreParams.HistoryLength 308 val EnableGHistDiff = coreParams.EnableGHistDiff 309 val UbtbGHRLength = coreParams.UbtbGHRLength 310 val UbtbSize = coreParams.UbtbSize 311 val EnableFauFTB = coreParams.EnableFauFTB 312 val FtbSize = coreParams.FtbSize 313 val FtbWays = coreParams.FtbWays 314 val RasSize = coreParams.RasSize 315 316 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 317 coreParams.branchPredictor(resp_in, p) 318 } 319 val numBr = coreParams.numBr 320 val TageTableInfos = coreParams.TageTableInfos 321 val TageBanks = coreParams.numBr 322 val SCNRows = coreParams.SCNRows 323 val SCCtrBits = coreParams.SCCtrBits 324 val SCHistLens = coreParams.SCHistLens 325 val SCNTables = coreParams.SCNTables 326 327 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 328 case ((n, cb), h) => (n, cb, h) 329 } 330 val ITTageTableInfos = coreParams.ITTageTableInfos 331 type FoldedHistoryInfo = Tuple2[Int, Int] 332 val foldedGHistInfos = 333 (TageTableInfos.map{ case (nRows, h, t) => 334 if (h > 0) 335 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 336 else 337 Set[FoldedHistoryInfo]() 338 }.reduce(_++_).toSet ++ 339 SCTableInfos.map{ case (nRows, _, h) => 340 if (h > 0) 341 Set((h, min(log2Ceil(nRows/TageBanks), h))) 342 else 343 Set[FoldedHistoryInfo]() 344 }.reduce(_++_).toSet ++ 345 ITTageTableInfos.map{ case (nRows, h, t) => 346 if (h > 0) 347 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 348 else 349 Set[FoldedHistoryInfo]() 350 }.reduce(_++_) ++ 351 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 352 ).toList 353 354 355 356 val CacheLineSize = coreParams.CacheLineSize 357 val CacheLineHalfWord = CacheLineSize / 16 358 val ExtHistoryLength = HistoryLength + 64 359 val IBufSize = coreParams.IBufSize 360 val DecodeWidth = coreParams.DecodeWidth 361 val RenameWidth = coreParams.RenameWidth 362 val CommitWidth = coreParams.CommitWidth 363 val FtqSize = coreParams.FtqSize 364 val IssQueSize = coreParams.IssQueSize 365 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 366 val NRPhyRegs = coreParams.NRPhyRegs 367 val PhyRegIdxWidth = log2Up(NRPhyRegs) 368 val RobSize = coreParams.RobSize 369 val IntRefCounterWidth = log2Ceil(RobSize) 370 val LoadQueueSize = coreParams.LoadQueueSize 371 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 372 val StoreQueueSize = coreParams.StoreQueueSize 373 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 374 val dpParams = coreParams.dpParams 375 val exuParameters = coreParams.exuParameters 376 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 377 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 378 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 379 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 380 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 381 val LoadPipelineWidth = coreParams.LoadPipelineWidth 382 val StorePipelineWidth = coreParams.StorePipelineWidth 383 val StoreBufferSize = coreParams.StoreBufferSize 384 val StoreBufferThreshold = coreParams.StoreBufferThreshold 385 val EnsbufferWidth = coreParams.EnsbufferWidth 386 val UncacheBufferSize = coreParams.UncacheBufferSize 387 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 388 val EnableFastForward = coreParams.EnableFastForward 389 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 390 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 391 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 392 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 393 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 394 val asidLen = coreParams.MMUAsidLen 395 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 396 val refillBothTlb = coreParams.refillBothTlb 397 val itlbParams = coreParams.itlbParameters 398 val ldtlbParams = coreParams.ldtlbParameters 399 val sttlbParams = coreParams.sttlbParameters 400 val btlbParams = coreParams.btlbParameters 401 val l2tlbParams = coreParams.l2tlbParameters 402 val NumPerfCounters = coreParams.NumPerfCounters 403 404 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 405 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 406 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 407 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 408 409 val instBytes = if (HasCExtension) 2 else 4 410 val instOffsetBits = log2Ceil(instBytes) 411 412 val icacheParameters = coreParams.icacheParameters 413 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 414 415 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 416 // for constrained LR/SC loop 417 val LRSCCycles = 64 418 // for lr storm 419 val LRSCBackOff = 8 420 421 // cache hierarchy configurations 422 val l1BusDataWidth = 256 423 424 // load violation predict 425 val ResetTimeMax2Pow = 20 //1078576 426 val ResetTimeMin2Pow = 10 //1024 427 // wait table parameters 428 val WaitTableSize = 1024 429 val MemPredPCWidth = log2Up(WaitTableSize) 430 val LWTUse2BitCounter = true 431 // store set parameters 432 val SSITSize = WaitTableSize 433 val LFSTSize = 32 434 val SSIDWidth = log2Up(LFSTSize) 435 val LFSTWidth = 4 436 val StoreSetEnable = true // LWT will be disabled if SS is enabled 437 438 val loadExuConfigs = coreParams.loadExuConfigs 439 val storeExuConfigs = coreParams.storeExuConfigs 440 441 val intExuConfigs = coreParams.intExuConfigs 442 443 val fpExuConfigs = coreParams.fpExuConfigs 444 445 val exuConfigs = coreParams.exuConfigs 446 447 val PCntIncrStep: Int = 6 448 val numPCntHc: Int = 25 449 val numPCntPtw: Int = 19 450 451 val numCSRPCntFrontend = 8 452 val numCSRPCntCtrl = 8 453 val numCSRPCntLsu = 8 454 val numCSRPCntHc = 5 455} 456