1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 HasMExtension: Boolean = true, 47 HasCExtension: Boolean = true, 48 HasDiv: Boolean = true, 49 HasICache: Boolean = true, 50 HasDCache: Boolean = true, 51 AddrBits: Int = 64, 52 VAddrBits: Int = 39, 53 HasFPU: Boolean = true, 54 HasCustomCSRCacheOp: Boolean = true, 55 FetchWidth: Int = 8, 56 AsidLength: Int = 16, 57 EnableBPU: Boolean = true, 58 EnableBPD: Boolean = true, 59 EnableRAS: Boolean = true, 60 EnableLB: Boolean = false, 61 EnableLoop: Boolean = true, 62 EnableSC: Boolean = true, 63 EnbaleTlbDebug: Boolean = false, 64 EnableJal: Boolean = false, 65 EnableFauFTB: Boolean = true, 66 UbtbGHRLength: Int = 4, 67 // HistoryLength: Int = 512, 68 EnableGHistDiff: Boolean = true, 69 UbtbSize: Int = 256, 70 FtbSize: Int = 2048, 71 RasSize: Int = 32, 72 CacheLineSize: Int = 512, 73 FtbWays: Int = 4, 74 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 75 // Sets Hist Tag 76 // Seq(( 2048, 2, 8), 77 // ( 2048, 9, 8), 78 // ( 2048, 13, 8), 79 // ( 2048, 20, 8), 80 // ( 2048, 26, 8), 81 // ( 2048, 44, 8), 82 // ( 2048, 73, 8), 83 // ( 2048, 256, 8)), 84 Seq(( 4096, 8, 8), 85 ( 4096, 13, 8), 86 ( 4096, 32, 8), 87 ( 4096, 119, 8)), 88 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 89 // Sets Hist Tag 90 Seq(( 256, 4, 9), 91 ( 256, 8, 9), 92 ( 512, 13, 9), 93 ( 512, 16, 9), 94 ( 512, 32, 9)), 95 SCNRows: Int = 512, 96 SCNTables: Int = 4, 97 SCCtrBits: Int = 6, 98 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 99 numBr: Int = 2, 100 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 101 ((resp_in: BranchPredictionResp, p: Parameters) => { 102 val ftb = Module(new FTB()(p)) 103 val ubtb =Module(new FauFTB()(p)) 104 // val bim = Module(new BIM()(p)) 105 val tage = Module(new Tage_SC()(p)) 106 val ras = Module(new RAS()(p)) 107 val ittage = Module(new ITTage()(p)) 108 val preds = Seq(ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 ubtb.io.in.bits.resp_in(0) := resp_in 117 tage.io.in.bits.resp_in(0) := ubtb.io.out 118 ftb.io.in.bits.resp_in(0) := tage.io.out 119 ittage.io.in.bits.resp_in(0) := ftb.io.out 120 ras.io.in.bits.resp_in(0) := ittage.io.out 121 122 (preds, ras.io.out) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 VirtualLoadQueueSize: Int = 80, 133 LoadQueueRARSize: Int = 80, 134 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 135 RollbackGroupSize: Int = 8, 136 LoadQueueReplaySize: Int = 80, 137 LoadUncacheBufferSize: Int = 20, 138 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 139 StoreQueueSize: Int = 64, 140 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 141 StoreQueueForwardWithMask: Boolean = true, 142 VlsQueueSize: Int = 8, 143 RobSize: Int = 256, 144 dpParams: DispatchParameters = DispatchParameters( 145 IntDqSize = 16, 146 FpDqSize = 16, 147 LsDqSize = 16, 148 IntDqDeqWidth = 4, 149 FpDqDeqWidth = 4, 150 LsDqDeqWidth = 4 151 ), 152 exuParameters: ExuParameters = ExuParameters( 153 JmpCnt = 1, 154 AluCnt = 4, 155 MulCnt = 0, 156 MduCnt = 2, 157 FmacCnt = 4, 158 FmiscCnt = 2, 159 FmiscDivSqrtCnt = 0, 160 LduCnt = 2, 161 StuCnt = 2 162 ), 163 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 164 LoadPipelineWidth: Int = 2, 165 StorePipelineWidth: Int = 2, 166 VecMemSrcInWidth: Int = 2, 167 VecMemInstWbWidth: Int = 1, 168 VecMemDispatchWidth: Int = 1, 169 StoreBufferSize: Int = 16, 170 StoreBufferThreshold: Int = 7, 171 EnsbufferWidth: Int = 2, 172 UncacheBufferSize: Int = 4, 173 EnableLoadToLoadForward: Boolean = true, 174 EnableFastForward: Boolean = false, 175 EnableLdVioCheckAfterReset: Boolean = true, 176 EnableSoftPrefetchAfterReset: Boolean = true, 177 EnableCacheErrorAfterReset: Boolean = true, 178 EnableDCacheWPU: Boolean = false, 179 EnableAccurateLoadError: Boolean = true, 180 EnableUncacheWriteOutstanding: Boolean = false, 181 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 182 ReSelectLen: Int = 7, // load replay queue replay select counter len 183 itlbParameters: TLBParameters = TLBParameters( 184 name = "itlb", 185 fetchi = true, 186 useDmode = false, 187 normalNWays = 32, 188 normalReplacer = Some("plru"), 189 superNWays = 4, 190 superReplacer = Some("plru") 191 ), 192 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 193 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 194 ldtlbParameters: TLBParameters = TLBParameters( 195 name = "ldtlb", 196 normalNSets = 64, 197 normalNWays = 1, 198 normalAssociative = "sa", 199 normalReplacer = Some("setplru"), 200 superNWays = 16, 201 normalAsVictim = true, 202 outReplace = false, 203 partialStaticPMP = true, 204 outsideRecvFlush = true, 205 saveLevel = true 206 ), 207 sttlbParameters: TLBParameters = TLBParameters( 208 name = "sttlb", 209 normalNSets = 64, 210 normalNWays = 1, 211 normalAssociative = "sa", 212 normalReplacer = Some("setplru"), 213 superNWays = 16, 214 normalAsVictim = true, 215 outReplace = false, 216 partialStaticPMP = true, 217 outsideRecvFlush = true, 218 saveLevel = true 219 ), 220 pftlbParameters: TLBParameters = TLBParameters( 221 name = "pftlb", 222 normalNSets = 64, 223 normalNWays = 1, 224 normalAssociative = "sa", 225 normalReplacer = Some("setplru"), 226 superNWays = 16, 227 normalAsVictim = true, 228 outReplace = false, 229 partialStaticPMP = true, 230 outsideRecvFlush = true, 231 saveLevel = true 232 ), 233 refillBothTlb: Boolean = false, 234 btlbParameters: TLBParameters = TLBParameters( 235 name = "btlb", 236 normalNSets = 1, 237 normalNWays = 64, 238 superNWays = 4, 239 ), 240 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 241 NumPerfCounters: Int = 16, 242 icacheParameters: ICacheParameters = ICacheParameters( 243 tagECC = Some("parity"), 244 dataECC = Some("parity"), 245 replacer = Some("setplru"), 246 nMissEntries = 2, 247 nProbeEntries = 2, 248 nPrefetchEntries = 12, 249 nPrefBufferEntries = 64, 250 hasPrefetch = true, 251 ), 252 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 253 tagECC = Some("secded"), 254 dataECC = Some("secded"), 255 replacer = Some("setplru"), 256 nMissEntries = 16, 257 nProbeEntries = 8, 258 nReleaseEntries = 18 259 )), 260 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 261 name = "l2", 262 level = 2, 263 ways = 8, 264 sets = 1024, // default 512KB L2 265 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 266 )), 267 L2NBanks: Int = 1, 268 usePTWRepeater: Boolean = false, 269 softTLB: Boolean = false, // dpi-c l1tlb debug only 270 softPTW: Boolean = false, // dpi-c l2tlb debug only 271 softPTWDelay: Int = 1 272){ 273 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 274 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 275 276 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 277 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 278 279 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 280 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 281 282 val fpExuConfigs = 283 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 284 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 285 286 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 287} 288 289case object DebugOptionsKey extends Field[DebugOptions] 290 291case class DebugOptions 292( 293 FPGAPlatform: Boolean = false, 294 EnableDifftest: Boolean = false, 295 AlwaysBasicDiff: Boolean = true, 296 EnableDebug: Boolean = false, 297 EnablePerfDebug: Boolean = true, 298 UseDRAMSim: Boolean = false, 299 EnableConstantin: Boolean = false, 300 EnableTopDown: Boolean = false 301) 302 303trait HasXSParameter { 304 305 implicit val p: Parameters 306 307 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 308 309 val coreParams = p(XSCoreParamsKey) 310 val env = p(DebugOptionsKey) 311 312 val XLEN = coreParams.XLEN 313 val minFLen = 32 314 val fLen = 64 315 def xLen = XLEN 316 317 val HasMExtension = coreParams.HasMExtension 318 val HasCExtension = coreParams.HasCExtension 319 val HasDiv = coreParams.HasDiv 320 val HasIcache = coreParams.HasICache 321 val HasDcache = coreParams.HasDCache 322 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 323 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 324 val AsidLength = coreParams.AsidLength 325 val ReSelectLen = coreParams.ReSelectLen 326 val AddrBytes = AddrBits / 8 // unused 327 val DataBits = XLEN 328 val DataBytes = DataBits / 8 329 val HasFPU = coreParams.HasFPU 330 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 331 val FetchWidth = coreParams.FetchWidth 332 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 333 val EnableBPU = coreParams.EnableBPU 334 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 335 val EnableRAS = coreParams.EnableRAS 336 val EnableLB = coreParams.EnableLB 337 val EnableLoop = coreParams.EnableLoop 338 val EnableSC = coreParams.EnableSC 339 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 340 val HistoryLength = coreParams.HistoryLength 341 val EnableGHistDiff = coreParams.EnableGHistDiff 342 val UbtbGHRLength = coreParams.UbtbGHRLength 343 val UbtbSize = coreParams.UbtbSize 344 val EnableFauFTB = coreParams.EnableFauFTB 345 val FtbSize = coreParams.FtbSize 346 val FtbWays = coreParams.FtbWays 347 val RasSize = coreParams.RasSize 348 349 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 350 coreParams.branchPredictor(resp_in, p) 351 } 352 val numBr = coreParams.numBr 353 val TageTableInfos = coreParams.TageTableInfos 354 val TageBanks = coreParams.numBr 355 val SCNRows = coreParams.SCNRows 356 val SCCtrBits = coreParams.SCCtrBits 357 val SCHistLens = coreParams.SCHistLens 358 val SCNTables = coreParams.SCNTables 359 360 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 361 case ((n, cb), h) => (n, cb, h) 362 } 363 val ITTageTableInfos = coreParams.ITTageTableInfos 364 type FoldedHistoryInfo = Tuple2[Int, Int] 365 val foldedGHistInfos = 366 (TageTableInfos.map{ case (nRows, h, t) => 367 if (h > 0) 368 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 369 else 370 Set[FoldedHistoryInfo]() 371 }.reduce(_++_).toSet ++ 372 SCTableInfos.map{ case (nRows, _, h) => 373 if (h > 0) 374 Set((h, min(log2Ceil(nRows/TageBanks), h))) 375 else 376 Set[FoldedHistoryInfo]() 377 }.reduce(_++_).toSet ++ 378 ITTageTableInfos.map{ case (nRows, h, t) => 379 if (h > 0) 380 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 381 else 382 Set[FoldedHistoryInfo]() 383 }.reduce(_++_) ++ 384 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 385 ).toList 386 387 388 389 val CacheLineSize = coreParams.CacheLineSize 390 val CacheLineHalfWord = CacheLineSize / 16 391 val ExtHistoryLength = HistoryLength + 64 392 val IBufSize = coreParams.IBufSize 393 val DecodeWidth = coreParams.DecodeWidth 394 val RenameWidth = coreParams.RenameWidth 395 val CommitWidth = coreParams.CommitWidth 396 val FtqSize = coreParams.FtqSize 397 val IssQueSize = coreParams.IssQueSize 398 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 399 val NRPhyRegs = coreParams.NRPhyRegs 400 val PhyRegIdxWidth = log2Up(NRPhyRegs) 401 val RobSize = coreParams.RobSize 402 val IntRefCounterWidth = log2Ceil(RobSize) 403 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 404 val LoadQueueRARSize = coreParams.LoadQueueRARSize 405 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 406 val RollbackGroupSize = coreParams.RollbackGroupSize 407 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 408 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 409 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 410 val StoreQueueSize = coreParams.StoreQueueSize 411 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 412 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 413 val VlsQueueSize = coreParams.VlsQueueSize 414 val dpParams = coreParams.dpParams 415 val exuParameters = coreParams.exuParameters 416 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 417 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 418 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 419 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 420 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 421 val LoadPipelineWidth = coreParams.LoadPipelineWidth 422 val StorePipelineWidth = coreParams.StorePipelineWidth 423 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 424 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 425 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 426 val StoreBufferSize = coreParams.StoreBufferSize 427 val StoreBufferThreshold = coreParams.StoreBufferThreshold 428 val EnsbufferWidth = coreParams.EnsbufferWidth 429 val UncacheBufferSize = coreParams.UncacheBufferSize 430 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 431 val EnableFastForward = coreParams.EnableFastForward 432 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 433 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 434 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 435 val EnableDCacheWPU = coreParams.EnableDCacheWPU 436 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 437 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 438 val asidLen = coreParams.MMUAsidLen 439 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 440 val refillBothTlb = coreParams.refillBothTlb 441 val itlbParams = coreParams.itlbParameters 442 val ldtlbParams = coreParams.ldtlbParameters 443 val sttlbParams = coreParams.sttlbParameters 444 val pftlbParams = coreParams.pftlbParameters 445 val btlbParams = coreParams.btlbParameters 446 val l2tlbParams = coreParams.l2tlbParameters 447 val NumPerfCounters = coreParams.NumPerfCounters 448 449 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 450 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 451 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 452 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 453 454 val instBytes = if (HasCExtension) 2 else 4 455 val instOffsetBits = log2Ceil(instBytes) 456 457 val icacheParameters = coreParams.icacheParameters 458 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 459 460 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 461 // for constrained LR/SC loop 462 val LRSCCycles = 64 463 // for lr storm 464 val LRSCBackOff = 8 465 466 // cache hierarchy configurations 467 val l1BusDataWidth = 256 468 469 // load violation predict 470 val ResetTimeMax2Pow = 20 //1078576 471 val ResetTimeMin2Pow = 10 //1024 472 // wait table parameters 473 val WaitTableSize = 1024 474 val MemPredPCWidth = log2Up(WaitTableSize) 475 val LWTUse2BitCounter = true 476 // store set parameters 477 val SSITSize = WaitTableSize 478 val LFSTSize = 32 479 val SSIDWidth = log2Up(LFSTSize) 480 val LFSTWidth = 4 481 val StoreSetEnable = true // LWT will be disabled if SS is enabled 482 val loadExuConfigs = coreParams.loadExuConfigs 483 val storeExuConfigs = coreParams.storeExuConfigs 484 485 val intExuConfigs = coreParams.intExuConfigs 486 487 val fpExuConfigs = coreParams.fpExuConfigs 488 489 val exuConfigs = coreParams.exuConfigs 490 491 val PCntIncrStep: Int = 6 492 val numPCntHc: Int = 25 493 val numPCntPtw: Int = 19 494 495 val numCSRPCntFrontend = 8 496 val numCSRPCntCtrl = 8 497 val numCSRPCntLsu = 8 498 val numCSRPCntHc = 5 499} 500