xref: /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala (revision 3c02ee8f82edea481fa8336c7f54ffc17fafba91) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16package xiangshan.frontend
17
18import chipsalliance.rocketchip.config.Parameters
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import chisel3.experimental.chiselName
25import xiangshan.cache.mmu.CAMTemplate
26
27class WrBypass[T <: Data](gen: T, val numEntries: Int, val idxWidth: Int,
28  val numWays: Int = 1, val tagWidth: Int = 0)(implicit p: Parameters) extends XSModule {
29  require(numEntries >= 0)
30  require(idxWidth > 0)
31  require(numWays >= 1)
32  require(tagWidth >= 0)
33  def hasTag = tagWidth > 0
34  def multipleWays = numWays > 1
35  val io = IO(new Bundle {
36    val wen = Input(Bool())
37    val write_idx = Input(UInt(idxWidth.W))
38    val write_tag = if (hasTag) Some(Input(UInt(tagWidth.W))) else None
39    val write_data = Input(Vec(numWays, gen))
40    val write_way_mask = if (multipleWays) Some(Input(Vec(numWays, Bool()))) else None
41
42    val hit = Output(Bool())
43    val hit_data = Vec(numWays, Valid(gen))
44  })
45
46  class WrBypassPtr extends CircularQueuePtr[WrBypassPtr](numEntries){
47  }
48
49  class Idx_Tag extends Bundle {
50    val idx = UInt(idxWidth.W)
51    val tag = if (hasTag) Some(UInt(tagWidth.W)) else None
52    def apply(idx: UInt, tag: UInt) = {
53      this.idx := idx
54      this.tag.map(_ := tag)
55    }
56  }
57  val idx_tag_cam = Module(new CAMTemplate(new Idx_Tag, numEntries, 1))
58  val data_mem = Mem(numEntries, Vec(numWays, gen))
59
60  val valids = RegInit(0.U.asTypeOf(Vec(numEntries, Vec(numWays, Bool()))))
61  val ever_written = RegInit(0.U.asTypeOf(Vec(numEntries, Bool())))
62
63  val enq_ptr = RegInit(0.U.asTypeOf(new WrBypassPtr))
64  val enq_idx = enq_ptr.value
65
66  idx_tag_cam.io.r.req(0)(io.write_idx, io.write_tag.getOrElse(0.U))
67  val hits_oh = idx_tag_cam.io.r.resp(0).zip(ever_written).map {case (h, ew) => h && ew}
68  val hit_idx = OHToUInt(hits_oh)
69  val hit = hits_oh.reduce(_||_)
70
71  io.hit := hit
72  for (i <- 0 until numWays) {
73    io.hit_data(i).valid := Mux1H(hits_oh, valids)(i)
74    io.hit_data(i).bits  := data_mem.read(hit_idx)(i)
75  }
76
77  val full_mask = Fill(numWays, 1.U(1.W)).asTypeOf(Vec(numWays, Bool()))
78  val update_way_mask = io.write_way_mask.getOrElse(full_mask)
79
80  // write data on every request
81  when (io.wen) {
82    val data_write_idx = Mux(hit, hit_idx, enq_idx)
83    data_mem.write(data_write_idx, io.write_data, update_way_mask)
84  }
85
86  // update valids
87  for (i <- 0 until numWays) {
88    when (io.wen) {
89      when (hit) {
90        when (update_way_mask(i)) {
91          valids(hit_idx)(i) := true.B
92        }
93      }.otherwise {
94        ever_written(enq_idx) := true.B
95        valids(enq_idx)(i) := false.B
96        when (update_way_mask(i)) {
97          valids(enq_idx)(i) := true.B
98        }
99      }
100    }
101  }
102
103  val enq_en = io.wen && !hit
104  idx_tag_cam.io.w.valid := enq_en
105  idx_tag_cam.io.w.bits.index := enq_idx
106  idx_tag_cam.io.w.bits.data(io.write_idx, io.write_tag.getOrElse(0.U))
107  enq_ptr := enq_ptr + enq_en
108
109  XSPerfAccumulate("wrbypass_hit",  io.wen &&  hit)
110  XSPerfAccumulate("wrbypass_miss", io.wen && !hit)
111
112  XSDebug(io.wen && hit,  p"wrbypass hit entry #${hit_idx}, idx ${io.write_idx}" +
113    p"tag ${io.write_tag.getOrElse(0.U)}data ${io.write_data}\n")
114  XSDebug(io.wen && !hit, p"wrbypass enq entry #${enq_idx}, idx ${io.write_idx}" +
115    p"tag ${io.write_tag.getOrElse(0.U)}data ${io.write_data}\n")
116}
117