1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import coupledL2._ 34import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 35 36import scala.math.min 37 38case object XSTileKey extends Field[Seq[XSCoreParameters]] 39 40case object XSCoreParamsKey extends Field[XSCoreParameters] 41 42case class XSCoreParameters 43( 44 HasPrefetch: Boolean = false, 45 HartId: Int = 0, 46 XLEN: Int = 64, 47 HasMExtension: Boolean = true, 48 HasCExtension: Boolean = true, 49 HasDiv: Boolean = true, 50 HasICache: Boolean = true, 51 HasDCache: Boolean = true, 52 AddrBits: Int = 64, 53 VAddrBits: Int = 39, 54 HasFPU: Boolean = true, 55 HasCustomCSRCacheOp: Boolean = true, 56 FetchWidth: Int = 8, 57 AsidLength: Int = 16, 58 EnableBPU: Boolean = true, 59 EnableBPD: Boolean = true, 60 EnableRAS: Boolean = true, 61 EnableLB: Boolean = false, 62 EnableLoop: Boolean = true, 63 EnableSC: Boolean = true, 64 EnbaleTlbDebug: Boolean = false, 65 EnableJal: Boolean = false, 66 EnableFauFTB: Boolean = true, 67 UbtbGHRLength: Int = 4, 68 // HistoryLength: Int = 512, 69 EnableGHistDiff: Boolean = true, 70 EnableCommitGHistDiff: Boolean = true, 71 UbtbSize: Int = 256, 72 FtbSize: Int = 2048, 73 RasSize: Int = 32, 74 CacheLineSize: Int = 512, 75 FtbWays: Int = 4, 76 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 77 // Sets Hist Tag 78 // Seq(( 2048, 2, 8), 79 // ( 2048, 9, 8), 80 // ( 2048, 13, 8), 81 // ( 2048, 20, 8), 82 // ( 2048, 26, 8), 83 // ( 2048, 44, 8), 84 // ( 2048, 73, 8), 85 // ( 2048, 256, 8)), 86 Seq(( 4096, 8, 8), 87 ( 4096, 13, 8), 88 ( 4096, 32, 8), 89 ( 4096, 119, 8)), 90 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 Seq(( 256, 4, 9), 93 ( 256, 8, 9), 94 ( 512, 13, 9), 95 ( 512, 16, 9), 96 ( 512, 32, 9)), 97 SCNRows: Int = 512, 98 SCNTables: Int = 4, 99 SCCtrBits: Int = 6, 100 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 101 numBr: Int = 2, 102 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 103 ((resp_in: BranchPredictionResp, p: Parameters) => { 104 val ftb = Module(new FTB()(p)) 105 val ubtb =Module(new FauFTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 val preds = Seq(ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 ubtb.io.in.bits.resp_in(0) := resp_in 119 tage.io.in.bits.resp_in(0) := ubtb.io.out 120 ftb.io.in.bits.resp_in(0) := tage.io.out 121 ittage.io.in.bits.resp_in(0) := ftb.io.out 122 ras.io.in.bits.resp_in(0) := ittage.io.out 123 124 (preds, ras.io.out) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 FtqSize: Int = 64, 131 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 132 IssQueSize: Int = 16, 133 NRPhyRegs: Int = 192, 134 VirtualLoadQueueSize: Int = 80, 135 LoadQueueRARSize: Int = 80, 136 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 137 RollbackGroupSize: Int = 8, 138 LoadQueueReplaySize: Int = 80, 139 LoadUncacheBufferSize: Int = 20, 140 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 141 StoreQueueSize: Int = 64, 142 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 143 StoreQueueForwardWithMask: Boolean = true, 144 VlsQueueSize: Int = 8, 145 RobSize: Int = 256, 146 dpParams: DispatchParameters = DispatchParameters( 147 IntDqSize = 16, 148 FpDqSize = 16, 149 LsDqSize = 16, 150 IntDqDeqWidth = 4, 151 FpDqDeqWidth = 4, 152 LsDqDeqWidth = 4 153 ), 154 exuParameters: ExuParameters = ExuParameters( 155 JmpCnt = 1, 156 AluCnt = 4, 157 MulCnt = 0, 158 MduCnt = 2, 159 FmacCnt = 4, 160 FmiscCnt = 2, 161 FmiscDivSqrtCnt = 0, 162 LduCnt = 2, 163 StuCnt = 2 164 ), 165 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 166 LoadPipelineWidth: Int = 2, 167 StorePipelineWidth: Int = 2, 168 VecMemSrcInWidth: Int = 2, 169 VecMemInstWbWidth: Int = 1, 170 VecMemDispatchWidth: Int = 1, 171 StoreBufferSize: Int = 16, 172 StoreBufferThreshold: Int = 7, 173 EnsbufferWidth: Int = 2, 174 UncacheBufferSize: Int = 4, 175 EnableLoadToLoadForward: Boolean = true, 176 EnableFastForward: Boolean = false, 177 EnableLdVioCheckAfterReset: Boolean = true, 178 EnableSoftPrefetchAfterReset: Boolean = true, 179 EnableCacheErrorAfterReset: Boolean = true, 180 EnableDCacheWPU: Boolean = false, 181 EnableAccurateLoadError: Boolean = true, 182 EnableUncacheWriteOutstanding: Boolean = false, 183 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 184 ReSelectLen: Int = 7, // load replay queue replay select counter len 185 itlbParameters: TLBParameters = TLBParameters( 186 name = "itlb", 187 fetchi = true, 188 useDmode = false, 189 normalNWays = 32, 190 normalReplacer = Some("plru"), 191 superNWays = 4, 192 superReplacer = Some("plru") 193 ), 194 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 195 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 196 ldtlbParameters: TLBParameters = TLBParameters( 197 name = "ldtlb", 198 normalNSets = 64, 199 normalNWays = 1, 200 normalAssociative = "sa", 201 normalReplacer = Some("setplru"), 202 superNWays = 16, 203 normalAsVictim = true, 204 outReplace = false, 205 partialStaticPMP = true, 206 outsideRecvFlush = true, 207 saveLevel = true 208 ), 209 sttlbParameters: TLBParameters = TLBParameters( 210 name = "sttlb", 211 normalNSets = 64, 212 normalNWays = 1, 213 normalAssociative = "sa", 214 normalReplacer = Some("setplru"), 215 superNWays = 16, 216 normalAsVictim = true, 217 outReplace = false, 218 partialStaticPMP = true, 219 outsideRecvFlush = true, 220 saveLevel = true 221 ), 222 pftlbParameters: TLBParameters = TLBParameters( 223 name = "pftlb", 224 normalNSets = 64, 225 normalNWays = 1, 226 normalAssociative = "sa", 227 normalReplacer = Some("setplru"), 228 superNWays = 16, 229 normalAsVictim = true, 230 outReplace = false, 231 partialStaticPMP = true, 232 outsideRecvFlush = true, 233 saveLevel = true 234 ), 235 refillBothTlb: Boolean = false, 236 btlbParameters: TLBParameters = TLBParameters( 237 name = "btlb", 238 normalNSets = 1, 239 normalNWays = 64, 240 superNWays = 4, 241 ), 242 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 243 NumPerfCounters: Int = 16, 244 icacheParameters: ICacheParameters = ICacheParameters( 245 tagECC = Some("parity"), 246 dataECC = Some("parity"), 247 replacer = Some("setplru"), 248 nMissEntries = 2, 249 nProbeEntries = 2, 250 nPrefetchEntries = 12, 251 nPrefBufferEntries = 64, 252 hasPrefetch = true, 253 ), 254 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 255 tagECC = Some("secded"), 256 dataECC = Some("secded"), 257 replacer = Some("setplru"), 258 nMissEntries = 16, 259 nProbeEntries = 8, 260 nReleaseEntries = 18 261 )), 262 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 263 name = "l2", 264 ways = 8, 265 sets = 1024, // default 512KB L2 266 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 267 )), 268 L2NBanks: Int = 1, 269 usePTWRepeater: Boolean = false, 270 softTLB: Boolean = false, // dpi-c l1tlb debug only 271 softPTW: Boolean = false, // dpi-c l2tlb debug only 272 softPTWDelay: Int = 1 273){ 274 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 275 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 276 277 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 278 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 279 280 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 281 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 282 283 val fpExuConfigs = 284 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 285 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 286 287 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 288} 289 290case object DebugOptionsKey extends Field[DebugOptions] 291 292case class DebugOptions 293( 294 FPGAPlatform: Boolean = false, 295 EnableDifftest: Boolean = false, 296 AlwaysBasicDiff: Boolean = true, 297 EnableDebug: Boolean = false, 298 EnablePerfDebug: Boolean = true, 299 UseDRAMSim: Boolean = false, 300 EnableConstantin: Boolean = false, 301 EnableTopDown: Boolean = false 302) 303 304trait HasXSParameter { 305 306 implicit val p: Parameters 307 308 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 309 310 val coreParams = p(XSCoreParamsKey) 311 val env = p(DebugOptionsKey) 312 313 val XLEN = coreParams.XLEN 314 val minFLen = 32 315 val fLen = 64 316 def xLen = XLEN 317 318 val HasMExtension = coreParams.HasMExtension 319 val HasCExtension = coreParams.HasCExtension 320 val HasDiv = coreParams.HasDiv 321 val HasIcache = coreParams.HasICache 322 val HasDcache = coreParams.HasDCache 323 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 324 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 325 val AsidLength = coreParams.AsidLength 326 val ReSelectLen = coreParams.ReSelectLen 327 val AddrBytes = AddrBits / 8 // unused 328 val DataBits = XLEN 329 val DataBytes = DataBits / 8 330 val HasFPU = coreParams.HasFPU 331 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 332 val FetchWidth = coreParams.FetchWidth 333 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 334 val EnableBPU = coreParams.EnableBPU 335 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 336 val EnableRAS = coreParams.EnableRAS 337 val EnableLB = coreParams.EnableLB 338 val EnableLoop = coreParams.EnableLoop 339 val EnableSC = coreParams.EnableSC 340 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 341 val HistoryLength = coreParams.HistoryLength 342 val EnableGHistDiff = coreParams.EnableGHistDiff 343 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 344 val UbtbGHRLength = coreParams.UbtbGHRLength 345 val UbtbSize = coreParams.UbtbSize 346 val EnableFauFTB = coreParams.EnableFauFTB 347 val FtbSize = coreParams.FtbSize 348 val FtbWays = coreParams.FtbWays 349 val RasSize = coreParams.RasSize 350 351 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 352 coreParams.branchPredictor(resp_in, p) 353 } 354 val numBr = coreParams.numBr 355 val TageTableInfos = coreParams.TageTableInfos 356 val TageBanks = coreParams.numBr 357 val SCNRows = coreParams.SCNRows 358 val SCCtrBits = coreParams.SCCtrBits 359 val SCHistLens = coreParams.SCHistLens 360 val SCNTables = coreParams.SCNTables 361 362 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 363 case ((n, cb), h) => (n, cb, h) 364 } 365 val ITTageTableInfos = coreParams.ITTageTableInfos 366 type FoldedHistoryInfo = Tuple2[Int, Int] 367 val foldedGHistInfos = 368 (TageTableInfos.map{ case (nRows, h, t) => 369 if (h > 0) 370 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 371 else 372 Set[FoldedHistoryInfo]() 373 }.reduce(_++_).toSet ++ 374 SCTableInfos.map{ case (nRows, _, h) => 375 if (h > 0) 376 Set((h, min(log2Ceil(nRows/TageBanks), h))) 377 else 378 Set[FoldedHistoryInfo]() 379 }.reduce(_++_).toSet ++ 380 ITTageTableInfos.map{ case (nRows, h, t) => 381 if (h > 0) 382 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 383 else 384 Set[FoldedHistoryInfo]() 385 }.reduce(_++_) ++ 386 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 387 ).toList 388 389 390 391 val CacheLineSize = coreParams.CacheLineSize 392 val CacheLineHalfWord = CacheLineSize / 16 393 val ExtHistoryLength = HistoryLength + 64 394 val IBufSize = coreParams.IBufSize 395 val DecodeWidth = coreParams.DecodeWidth 396 val RenameWidth = coreParams.RenameWidth 397 val CommitWidth = coreParams.CommitWidth 398 val FtqSize = coreParams.FtqSize 399 val IssQueSize = coreParams.IssQueSize 400 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 401 val NRPhyRegs = coreParams.NRPhyRegs 402 val PhyRegIdxWidth = log2Up(NRPhyRegs) 403 val RobSize = coreParams.RobSize 404 val IntRefCounterWidth = log2Ceil(RobSize) 405 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 406 val LoadQueueRARSize = coreParams.LoadQueueRARSize 407 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 408 val RollbackGroupSize = coreParams.RollbackGroupSize 409 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 410 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 411 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 412 val StoreQueueSize = coreParams.StoreQueueSize 413 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 414 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 415 val VlsQueueSize = coreParams.VlsQueueSize 416 val dpParams = coreParams.dpParams 417 val exuParameters = coreParams.exuParameters 418 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 419 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 420 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 421 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 422 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 423 val LoadPipelineWidth = coreParams.LoadPipelineWidth 424 val StorePipelineWidth = coreParams.StorePipelineWidth 425 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 426 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 427 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 428 val StoreBufferSize = coreParams.StoreBufferSize 429 val StoreBufferThreshold = coreParams.StoreBufferThreshold 430 val EnsbufferWidth = coreParams.EnsbufferWidth 431 val UncacheBufferSize = coreParams.UncacheBufferSize 432 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 433 val EnableFastForward = coreParams.EnableFastForward 434 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 435 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 436 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 437 val EnableDCacheWPU = coreParams.EnableDCacheWPU 438 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 439 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 440 val asidLen = coreParams.MMUAsidLen 441 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 442 val refillBothTlb = coreParams.refillBothTlb 443 val itlbParams = coreParams.itlbParameters 444 val ldtlbParams = coreParams.ldtlbParameters 445 val sttlbParams = coreParams.sttlbParameters 446 val pftlbParams = coreParams.pftlbParameters 447 val btlbParams = coreParams.btlbParameters 448 val l2tlbParams = coreParams.l2tlbParameters 449 val NumPerfCounters = coreParams.NumPerfCounters 450 451 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 452 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 453 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 454 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 455 456 val instBytes = if (HasCExtension) 2 else 4 457 val instOffsetBits = log2Ceil(instBytes) 458 459 val icacheParameters = coreParams.icacheParameters 460 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 461 462 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 463 // for constrained LR/SC loop 464 val LRSCCycles = 64 465 // for lr storm 466 val LRSCBackOff = 8 467 468 // cache hierarchy configurations 469 val l1BusDataWidth = 256 470 471 // load violation predict 472 val ResetTimeMax2Pow = 20 //1078576 473 val ResetTimeMin2Pow = 10 //1024 474 // wait table parameters 475 val WaitTableSize = 1024 476 val MemPredPCWidth = log2Up(WaitTableSize) 477 val LWTUse2BitCounter = true 478 // store set parameters 479 val SSITSize = WaitTableSize 480 val LFSTSize = 32 481 val SSIDWidth = log2Up(LFSTSize) 482 val LFSTWidth = 4 483 val StoreSetEnable = true // LWT will be disabled if SS is enabled 484 val LFSTEnable = false 485 val loadExuConfigs = coreParams.loadExuConfigs 486 val storeExuConfigs = coreParams.storeExuConfigs 487 488 val intExuConfigs = coreParams.intExuConfigs 489 490 val fpExuConfigs = coreParams.fpExuConfigs 491 492 val exuConfigs = coreParams.exuConfigs 493 494 val PCntIncrStep: Int = 6 495 val numPCntHc: Int = 25 496 val numPCntPtw: Int = 19 497 498 val numCSRPCntFrontend = 8 499 val numCSRPCntCtrl = 8 500 val numCSRPCntLsu = 8 501 val numCSRPCntHc = 5 502} 503