1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 46 47import scala.math.min 48 49case object XSTileKey extends Field[Seq[XSCoreParameters]] 50 51case object XSCoreParamsKey extends Field[XSCoreParameters] 52 53case class XSCoreParameters 54( 55 HasPrefetch: Boolean = false, 56 HartId: Int = 0, 57 XLEN: Int = 64, 58 VLEN: Int = 128, 59 ELEN: Int = 64, 60 HasMExtension: Boolean = true, 61 HasCExtension: Boolean = true, 62 HasDiv: Boolean = true, 63 HasICache: Boolean = true, 64 HasDCache: Boolean = true, 65 AddrBits: Int = 64, 66 VAddrBits: Int = 39, 67 HasFPU: Boolean = true, 68 HasVPU: Boolean = true, 69 HasCustomCSRCacheOp: Boolean = true, 70 FetchWidth: Int = 8, 71 AsidLength: Int = 16, 72 EnableBPU: Boolean = true, 73 EnableBPD: Boolean = true, 74 EnableRAS: Boolean = true, 75 EnableLB: Boolean = false, 76 EnableLoop: Boolean = true, 77 EnableSC: Boolean = true, 78 EnbaleTlbDebug: Boolean = false, 79 EnableJal: Boolean = false, 80 EnableFauFTB: Boolean = true, 81 UbtbGHRLength: Int = 4, 82 // HistoryLength: Int = 512, 83 EnableGHistDiff: Boolean = true, 84 EnableCommitGHistDiff: Boolean = true, 85 UbtbSize: Int = 256, 86 FtbSize: Int = 2048, 87 RasSize: Int = 32, 88 CacheLineSize: Int = 512, 89 FtbWays: Int = 4, 90 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 // Seq(( 2048, 2, 8), 93 // ( 2048, 9, 8), 94 // ( 2048, 13, 8), 95 // ( 2048, 20, 8), 96 // ( 2048, 26, 8), 97 // ( 2048, 44, 8), 98 // ( 2048, 73, 8), 99 // ( 2048, 256, 8)), 100 Seq(( 4096, 8, 8), 101 ( 4096, 13, 8), 102 ( 4096, 32, 8), 103 ( 4096, 119, 8)), 104 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 256, 4, 9), 107 ( 256, 8, 9), 108 ( 512, 13, 9), 109 ( 512, 16, 9), 110 ( 512, 32, 9)), 111 SCNRows: Int = 512, 112 SCNTables: Int = 4, 113 SCCtrBits: Int = 6, 114 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 115 numBr: Int = 2, 116 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 117 ((resp_in: BranchPredictionResp, p: Parameters) => { 118 val ftb = Module(new FTB()(p)) 119 val ubtb =Module(new FauFTB()(p)) 120 // val bim = Module(new BIM()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(ubtb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 // ubtb.io.resp_in(0) := resp_in 128 // bim.io.resp_in(0) := ubtb.io.resp 129 // btb.io.resp_in(0) := bim.io.resp 130 // tage.io.resp_in(0) := btb.io.resp 131 // loop.io.resp_in(0) := tage.io.resp 132 ubtb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := ubtb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }), 140 IBufSize: Int = 48, 141 DecodeWidth: Int = 6, 142 RenameWidth: Int = 6, 143 CommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 FtqSize: Int = 64, 146 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 147 IntLogicRegs: Int = 32, 148 FpLogicRegs: Int = 33, 149 VecLogicRegs: Int = 32 + 8 + 1, // 8: tmp, 1: vconfig 150 VCONFIG_IDX: Int = 40, 151 NRPhyRegs: Int = 192, 152 IntPhyRegs: Int = 192, 153 VfPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 80, 155 LoadQueueRARSize: Int = 80, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 80, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 256, 166 RabSize: Int = 256, 167 dpParams: DispatchParameters = DispatchParameters( 168 IntDqSize = 16, 169 FpDqSize = 16, 170 LsDqSize = 16, 171 IntDqDeqWidth = 6, 172 FpDqDeqWidth = 6, 173 LsDqDeqWidth = 6, 174 ), 175 intPreg: PregParams = IntPregParams( 176 numEntries = 64, 177 numRead = 14, 178 numWrite = 8, 179 ), 180 vfPreg: VfPregParams = VfPregParams( 181 numEntries = 64, 182 numRead = 14, 183 numWrite = 8, 184 ), 185 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 186 LoadPipelineWidth: Int = 2, 187 StorePipelineWidth: Int = 2, 188 VecMemSrcInWidth: Int = 2, 189 VecMemInstWbWidth: Int = 1, 190 VecMemDispatchWidth: Int = 1, 191 StoreBufferSize: Int = 16, 192 StoreBufferThreshold: Int = 7, 193 EnsbufferWidth: Int = 2, 194 UncacheBufferSize: Int = 4, 195 EnableLoadToLoadForward: Boolean = true, 196 EnableFastForward: Boolean = false, 197 EnableLdVioCheckAfterReset: Boolean = true, 198 EnableSoftPrefetchAfterReset: Boolean = true, 199 EnableCacheErrorAfterReset: Boolean = true, 200 EnableDCacheWPU: Boolean = false, 201 EnableAccurateLoadError: Boolean = true, 202 EnableUncacheWriteOutstanding: Boolean = false, 203 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 204 ReSelectLen: Int = 7, // load replay queue replay select counter len 205 itlbParameters: TLBParameters = TLBParameters( 206 name = "itlb", 207 fetchi = true, 208 useDmode = false, 209 normalNWays = 32, 210 normalReplacer = Some("plru"), 211 superNWays = 4, 212 superReplacer = Some("plru") 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 sttlbParameters: TLBParameters = TLBParameters( 230 name = "sttlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 pftlbParameters: TLBParameters = TLBParameters( 243 name = "pftlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 refillBothTlb: Boolean = false, 256 btlbParameters: TLBParameters = TLBParameters( 257 name = "btlb", 258 normalNSets = 1, 259 normalNWays = 64, 260 superNWays = 4, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 64, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 def intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 val pregBits = intPreg.addrWidth 302 val numRfRead = intPreg.numRead 303 val numRfWrite = intPreg.numWrite 304 SchdBlockParams(Seq( 305 IssueBlockParams(Seq( 306 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 307 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 308 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 311 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 312 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 315 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams(Seq(I2fCfg, VSetRiWiCfg, VSetRiWvfCfg), Seq(VecWB(port = 6, Int.MaxValue), IntWB(port = 7, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 319 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 320 ), 321 numPregs = intPreg.numEntries, 322 numRfReadWrite = Some((numRfRead, numRfWrite)), 323 numDeqOutside = 0, 324 schdType = schdType, 325 rfDataWidth = intPreg.dataCfg.dataWidth, 326 numUopIn = dpParams.IntDqDeqWidth, 327 ) 328 } 329 def vfSchdParams = { 330 implicit val schdType: SchedulerType = VfScheduler() 331 val pregBits = vfPreg.addrWidth 332 val numRfRead = vfPreg.numRead 333 val numRfWrite = vfPreg.numWrite 334 SchdBlockParams(Seq( 335 IssueBlockParams(Seq( 336 ExeUnitParams(Seq(VialuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 337 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 338 IssueBlockParams(Seq( 339 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 340 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 341 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 342 ), 343 numPregs = vfPreg.numEntries, 344 numRfReadWrite = Some((numRfRead, numRfWrite)), 345 numDeqOutside = 0, 346 schdType = schdType, 347 rfDataWidth = vfPreg.dataCfg.dataWidth, 348 numUopIn = dpParams.FpDqDeqWidth, 349 ) 350 } 351 def memSchdParams = { 352 implicit val schdType: SchedulerType = MemScheduler() 353 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 354 val rfDataWidth = 64 355 356 SchdBlockParams(Seq( 357 IssueBlockParams(Seq( 358 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 359 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 360 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 361 IssueBlockParams(Seq( 362 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 363 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 364 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 365 IssueBlockParams(Seq( 366 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 367 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 368 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 369 ), 370 numPregs = intPreg.numEntries max vfPreg.numEntries, 371 numRfReadWrite = None, 372 numDeqOutside = 0, 373 schdType = schdType, 374 rfDataWidth = rfDataWidth, 375 numUopIn = dpParams.LsDqDeqWidth, 376 ) 377 } 378 379 def backendParams: BackendParams = backend.BackendParams(Map( 380 IntScheduler() -> intSchdParams, 381 VfScheduler() -> vfSchdParams, 382 MemScheduler() -> memSchdParams, 383 ), Seq( 384 intPreg, 385 vfPreg, 386 )) 387} 388 389case object DebugOptionsKey extends Field[DebugOptions] 390 391case class DebugOptions 392( 393 FPGAPlatform: Boolean = false, 394 EnableDifftest: Boolean = false, 395 AlwaysBasicDiff: Boolean = true, 396 EnableDebug: Boolean = false, 397 EnablePerfDebug: Boolean = true, 398 UseDRAMSim: Boolean = false, 399 EnableConstantin: Boolean = false, 400 EnableTopDown: Boolean = false 401) 402 403trait HasXSParameter { 404 405 implicit val p: Parameters 406 407 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 408 409 val coreParams = p(XSCoreParamsKey) 410 val env = p(DebugOptionsKey) 411 412 val XLEN = coreParams.XLEN 413 val VLEN = coreParams.VLEN 414 val ELEN = coreParams.ELEN 415 val minFLen = 32 416 val fLen = 64 417 def xLen = XLEN 418 419 val HasMExtension = coreParams.HasMExtension 420 val HasCExtension = coreParams.HasCExtension 421 val HasDiv = coreParams.HasDiv 422 val HasIcache = coreParams.HasICache 423 val HasDcache = coreParams.HasDCache 424 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 425 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 426 val AsidLength = coreParams.AsidLength 427 val ReSelectLen = coreParams.ReSelectLen 428 val AddrBytes = AddrBits / 8 // unused 429 val DataBits = XLEN 430 val DataBytes = DataBits / 8 431 val HasFPU = coreParams.HasFPU 432 val HasVPU = coreParams.HasVPU 433 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 434 val FetchWidth = coreParams.FetchWidth 435 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 436 val EnableBPU = coreParams.EnableBPU 437 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 438 val EnableRAS = coreParams.EnableRAS 439 val EnableLB = coreParams.EnableLB 440 val EnableLoop = coreParams.EnableLoop 441 val EnableSC = coreParams.EnableSC 442 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 443 val HistoryLength = coreParams.HistoryLength 444 val EnableGHistDiff = coreParams.EnableGHistDiff 445 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 446 val UbtbGHRLength = coreParams.UbtbGHRLength 447 val UbtbSize = coreParams.UbtbSize 448 val EnableFauFTB = coreParams.EnableFauFTB 449 val FtbSize = coreParams.FtbSize 450 val FtbWays = coreParams.FtbWays 451 val RasSize = coreParams.RasSize 452 453 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 454 coreParams.branchPredictor(resp_in, p) 455 } 456 val numBr = coreParams.numBr 457 val TageTableInfos = coreParams.TageTableInfos 458 val TageBanks = coreParams.numBr 459 val SCNRows = coreParams.SCNRows 460 val SCCtrBits = coreParams.SCCtrBits 461 val SCHistLens = coreParams.SCHistLens 462 val SCNTables = coreParams.SCNTables 463 464 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 465 case ((n, cb), h) => (n, cb, h) 466 } 467 val ITTageTableInfos = coreParams.ITTageTableInfos 468 type FoldedHistoryInfo = Tuple2[Int, Int] 469 val foldedGHistInfos = 470 (TageTableInfos.map{ case (nRows, h, t) => 471 if (h > 0) 472 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 473 else 474 Set[FoldedHistoryInfo]() 475 }.reduce(_++_).toSet ++ 476 SCTableInfos.map{ case (nRows, _, h) => 477 if (h > 0) 478 Set((h, min(log2Ceil(nRows/TageBanks), h))) 479 else 480 Set[FoldedHistoryInfo]() 481 }.reduce(_++_).toSet ++ 482 ITTageTableInfos.map{ case (nRows, h, t) => 483 if (h > 0) 484 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 485 else 486 Set[FoldedHistoryInfo]() 487 }.reduce(_++_) ++ 488 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 489 ).toList 490 491 492 493 val CacheLineSize = coreParams.CacheLineSize 494 val CacheLineHalfWord = CacheLineSize / 16 495 val ExtHistoryLength = HistoryLength + 64 496 val IBufSize = coreParams.IBufSize 497 val DecodeWidth = coreParams.DecodeWidth 498 val RenameWidth = coreParams.RenameWidth 499 val CommitWidth = coreParams.CommitWidth 500 val MaxUopSize = coreParams.MaxUopSize 501 val FtqSize = coreParams.FtqSize 502 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 503 val IntLogicRegs = coreParams.IntLogicRegs 504 val FpLogicRegs = coreParams.FpLogicRegs 505 val VecLogicRegs = coreParams.VecLogicRegs 506 val VCONFIG_IDX = coreParams.VCONFIG_IDX 507 val NRPhyRegs = coreParams.NRPhyRegs 508 val PhyRegIdxWidth = log2Up(NRPhyRegs) 509 val IntPhyRegs = coreParams.IntPhyRegs 510 val VfPhyRegs = coreParams.VfPhyRegs 511 val IntPregIdxWidth = log2Up(IntPhyRegs) 512 val VfPregIdxWidth = log2Up(VfPhyRegs) 513 val RobSize = coreParams.RobSize 514 val RabSize = coreParams.RabSize 515 val IntRefCounterWidth = log2Ceil(RobSize) 516 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 517 val LoadQueueRARSize = coreParams.LoadQueueRARSize 518 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 519 val RollbackGroupSize = coreParams.RollbackGroupSize 520 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 521 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 522 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 523 val StoreQueueSize = coreParams.StoreQueueSize 524 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 525 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 526 val VlsQueueSize = coreParams.VlsQueueSize 527 val dpParams = coreParams.dpParams 528 529 def backendParams: BackendParams = coreParams.backendParams 530 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 531 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 532 val LoadPipelineWidth = coreParams.LoadPipelineWidth 533 val StorePipelineWidth = coreParams.StorePipelineWidth 534 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 535 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 536 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 537 val StoreBufferSize = coreParams.StoreBufferSize 538 val StoreBufferThreshold = coreParams.StoreBufferThreshold 539 val EnsbufferWidth = coreParams.EnsbufferWidth 540 val UncacheBufferSize = coreParams.UncacheBufferSize 541 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 542 val EnableFastForward = coreParams.EnableFastForward 543 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 544 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 545 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 546 val EnableDCacheWPU = coreParams.EnableDCacheWPU 547 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 548 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 549 val asidLen = coreParams.MMUAsidLen 550 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 551 val refillBothTlb = coreParams.refillBothTlb 552 val itlbParams = coreParams.itlbParameters 553 val ldtlbParams = coreParams.ldtlbParameters 554 val sttlbParams = coreParams.sttlbParameters 555 val pftlbParams = coreParams.pftlbParameters 556 val btlbParams = coreParams.btlbParameters 557 val l2tlbParams = coreParams.l2tlbParameters 558 val NumPerfCounters = coreParams.NumPerfCounters 559 560 val instBytes = if (HasCExtension) 2 else 4 561 val instOffsetBits = log2Ceil(instBytes) 562 563 val icacheParameters = coreParams.icacheParameters 564 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 565 566 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 567 // for constrained LR/SC loop 568 val LRSCCycles = 64 569 // for lr storm 570 val LRSCBackOff = 8 571 572 // cache hierarchy configurations 573 val l1BusDataWidth = 256 574 575 // load violation predict 576 val ResetTimeMax2Pow = 20 //1078576 577 val ResetTimeMin2Pow = 10 //1024 578 // wait table parameters 579 val WaitTableSize = 1024 580 val MemPredPCWidth = log2Up(WaitTableSize) 581 val LWTUse2BitCounter = true 582 // store set parameters 583 val SSITSize = WaitTableSize 584 val LFSTSize = 32 585 val SSIDWidth = log2Up(LFSTSize) 586 val LFSTWidth = 4 587 val StoreSetEnable = true // LWT will be disabled if SS is enabled 588 val PCntIncrStep: Int = 6 589 val numPCntHc: Int = 25 590 val numPCntPtw: Int = 19 591 592 val numCSRPCntFrontend = 8 593 val numCSRPCntCtrl = 8 594 val numCSRPCntLsu = 8 595 val numCSRPCntHc = 5 596} 597