1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, MemoryOpConstants, HasDCacheParameters} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30 31class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants with HasDCacheParameters{ 32 val io = IO(new Bundle() { 33 val hartId = Input(UInt(8.W)) 34 val in = Flipped(Decoupled(new ExuInput)) 35 val storeDataIn = Flipped(Valid(new ExuOutput)) // src2 from rs 36 val out = Decoupled(new ExuOutput) 37 val dcache = new AtomicWordIO 38 val dtlb = new TlbRequestIO(2) 39 val pmpResp = Flipped(new PMPRespBundle()) 40 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 41 val flush_sbuffer = new SbufferFlushBundle 42 val feedbackSlow = ValidIO(new RSFeedback) 43 val redirect = Flipped(ValidIO(new Redirect)) 44 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 45 val csrCtrl = Flipped(new CustomCSRCtrlIO) 46 }) 47 48 //------------------------------------------------------- 49 // Atomics Memory Accsess FSM 50 //------------------------------------------------------- 51 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 52 val state = RegInit(s_invalid) 53 val out_valid = RegInit(false.B) 54 val data_valid = RegInit(false.B) 55 val in = Reg(new ExuInput()) 56 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 57 val atom_override_xtval = RegInit(false.B) 58 val have_sent_first_tlb_req = RegInit(false.B) 59 val isLr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 60 // paddr after translation 61 val paddr = Reg(UInt()) 62 val vaddr = in.src(0) 63 val is_mmio = Reg(Bool()) 64 // pmp check 65 val static_pm = Reg(Valid(Bool())) // valid for static, bits for mmio 66 // dcache response data 67 val resp_data = Reg(UInt()) 68 val resp_data_wire = WireInit(0.U) 69 val is_lrsc_valid = Reg(Bool()) 70 // sbuffer is empty or not 71 val sbuffer_empty = io.flush_sbuffer.empty 72 73 74 // Difftest signals 75 val paddr_reg = Reg(UInt(64.W)) 76 val data_reg = Reg(UInt(64.W)) 77 val mask_reg = Reg(UInt(8.W)) 78 val fuop_reg = Reg(UInt(8.W)) 79 80 io.exceptionAddr.valid := atom_override_xtval 81 io.exceptionAddr.bits := in.src(0) 82 83 // assign default value to output signals 84 io.in.ready := false.B 85 86 io.dcache.req.valid := false.B 87 io.dcache.req.bits := DontCare 88 89 io.dtlb.req.valid := false.B 90 io.dtlb.req.bits := DontCare 91 io.dtlb.req_kill := false.B 92 io.dtlb.resp.ready := true.B 93 94 io.flush_sbuffer.valid := false.B 95 96 XSDebug("state: %d\n", state) 97 98 when (state === s_invalid) { 99 io.in.ready := true.B 100 when (io.in.fire) { 101 in := io.in.bits 102 in.src(1) := in.src(1) // leave src2 unchanged 103 state := s_tlb_and_flush_sbuffer_req 104 have_sent_first_tlb_req := false.B 105 } 106 } 107 108 when (io.storeDataIn.fire) { 109 in.src(1) := io.storeDataIn.bits.data 110 data_valid := true.B 111 } 112 113 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 114 115 // Send TLB feedback to store issue queue 116 // we send feedback right after we receives request 117 // also, we always treat amo as tlb hit 118 // since we will continue polling tlb all by ourself 119 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 120 io.feedbackSlow.bits.hit := true.B 121 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 122 io.feedbackSlow.bits.flushState := DontCare 123 io.feedbackSlow.bits.sourceType := DontCare 124 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 125 126 // tlb translation, manipulating signals && deal with exception 127 // at the same time, flush sbuffer 128 when (state === s_tlb_and_flush_sbuffer_req) { 129 // send req to dtlb 130 // keep firing until tlb hit 131 io.dtlb.req.valid := true.B 132 io.dtlb.req.bits.vaddr := in.src(0) 133 io.dtlb.resp.ready := true.B 134 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 135 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 136 io.dtlb.req.bits.debug.isFirstIssue := false.B 137 138 // send req to sbuffer to flush it if it is not empty 139 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 140 141 // do not accept tlb resp in the first cycle 142 // this limition is for hw prefetcher 143 // when !have_sent_first_tlb_req, tlb resp may come from hw prefetch 144 have_sent_first_tlb_req := true.B 145 146 when(io.dtlb.resp.fire && have_sent_first_tlb_req){ 147 paddr := io.dtlb.resp.bits.paddr(0) 148 // exception handling 149 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 150 "b00".U -> true.B, //b 151 "b01".U -> (in.src(0)(0) === 0.U), //h 152 "b10".U -> (in.src(0)(1,0) === 0.U), //w 153 "b11".U -> (in.src(0)(2,0) === 0.U) //d 154 )) 155 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 156 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 157 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 158 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 159 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 160 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 161 static_pm := io.dtlb.resp.bits.static_pm 162 163 when (!io.dtlb.resp.bits.miss) { 164 when (!addrAligned) { 165 // NOTE: when addrAligned, do not need to wait tlb actually 166 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 167 // if there are exceptions, no need to execute it 168 state := s_finish 169 out_valid := true.B 170 atom_override_xtval := true.B 171 } .otherwise { 172 state := s_pm 173 } 174 } 175 } 176 } 177 178 when (state === s_pm) { 179 val pmp = WireInit(io.pmpResp) 180 when (static_pm.valid) { 181 pmp.ld := false.B 182 pmp.st := false.B 183 pmp.instr := false.B 184 pmp.mmio := static_pm.bits 185 } 186 is_mmio := pmp.mmio 187 // NOTE: only handle load/store exception here, if other exception happens, don't send here 188 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 189 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 190 val exception_pa = pmp.st || pmp.ld 191 when (exception_va || exception_pa) { 192 state := s_finish 193 out_valid := true.B 194 atom_override_xtval := true.B 195 }.otherwise { 196 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 197 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 198 } 199 // update storeAccessFault bit 200 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || pmp.ld && isLr 201 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || pmp.ld && !isLr 202 } 203 204 when (state === s_wait_flush_sbuffer_resp) { 205 when (sbuffer_empty) { 206 state := s_cache_req 207 } 208 } 209 210 when (state === s_cache_req) { 211 val pipe_req = io.dcache.req.bits 212 pipe_req := DontCare 213 214 pipe_req.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 215 LSUOpType.lr_w -> M_XLR, 216 LSUOpType.sc_w -> M_XSC, 217 LSUOpType.amoswap_w -> M_XA_SWAP, 218 LSUOpType.amoadd_w -> M_XA_ADD, 219 LSUOpType.amoxor_w -> M_XA_XOR, 220 LSUOpType.amoand_w -> M_XA_AND, 221 LSUOpType.amoor_w -> M_XA_OR, 222 LSUOpType.amomin_w -> M_XA_MIN, 223 LSUOpType.amomax_w -> M_XA_MAX, 224 LSUOpType.amominu_w -> M_XA_MINU, 225 LSUOpType.amomaxu_w -> M_XA_MAXU, 226 227 LSUOpType.lr_d -> M_XLR, 228 LSUOpType.sc_d -> M_XSC, 229 LSUOpType.amoswap_d -> M_XA_SWAP, 230 LSUOpType.amoadd_d -> M_XA_ADD, 231 LSUOpType.amoxor_d -> M_XA_XOR, 232 LSUOpType.amoand_d -> M_XA_AND, 233 LSUOpType.amoor_d -> M_XA_OR, 234 LSUOpType.amomin_d -> M_XA_MIN, 235 LSUOpType.amomax_d -> M_XA_MAX, 236 LSUOpType.amominu_d -> M_XA_MINU, 237 LSUOpType.amomaxu_d -> M_XA_MAXU 238 )) 239 pipe_req.miss := false.B 240 pipe_req.probe := false.B 241 pipe_req.probe_need_data := false.B 242 pipe_req.source := AMO_SOURCE.U 243 pipe_req.addr := get_block_addr(paddr) 244 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 245 pipe_req.word_idx := get_word(paddr) 246 pipe_req.amo_data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 247 pipe_req.amo_mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 248 249 io.dcache.req.valid := Mux( 250 io.dcache.req.bits.cmd === M_XLR, 251 !io.dcache.block_lr, // block lr to survive in lr storm 252 data_valid // wait until src(1) is ready 253 ) 254 255 when(io.dcache.req.fire){ 256 state := s_cache_resp 257 paddr_reg := paddr 258 data_reg := io.dcache.req.bits.amo_data 259 mask_reg := io.dcache.req.bits.amo_mask 260 fuop_reg := in.uop.ctrl.fuOpType 261 } 262 } 263 264 val dcache_resp_data = Reg(UInt()) 265 val dcache_resp_id = Reg(UInt()) 266 val dcache_resp_error = Reg(Bool()) 267 268 when (state === s_cache_resp) { 269 // when not miss 270 // everything is OK, simply send response back to sbuffer 271 // when miss and not replay 272 // wait for missQueue to handling miss and replaying our request 273 // when miss and replay 274 // req missed and fail to enter missQueue, manually replay it later 275 // TODO: add assertions: 276 // 1. add a replay delay counter? 277 // 2. when req gets into MissQueue, it should not miss any more 278 when(io.dcache.resp.fire()) { 279 when(io.dcache.resp.bits.miss) { 280 when(io.dcache.resp.bits.replay) { 281 state := s_cache_req 282 } 283 } .otherwise { 284 dcache_resp_data := io.dcache.resp.bits.data 285 dcache_resp_id := io.dcache.resp.bits.id 286 dcache_resp_error := io.dcache.resp.bits.error 287 state := s_cache_resp_latch 288 } 289 } 290 } 291 292 when (state === s_cache_resp_latch) { 293 is_lrsc_valid := dcache_resp_id 294 val rdataSel = LookupTree(paddr(2, 0), List( 295 "b000".U -> dcache_resp_data(63, 0), 296 "b001".U -> dcache_resp_data(63, 8), 297 "b010".U -> dcache_resp_data(63, 16), 298 "b011".U -> dcache_resp_data(63, 24), 299 "b100".U -> dcache_resp_data(63, 32), 300 "b101".U -> dcache_resp_data(63, 40), 301 "b110".U -> dcache_resp_data(63, 48), 302 "b111".U -> dcache_resp_data(63, 56) 303 )) 304 305 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 306 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 307 LSUOpType.sc_w -> dcache_resp_data, 308 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 309 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 310 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 311 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 312 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 313 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 314 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 315 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 316 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 317 318 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 319 LSUOpType.sc_d -> dcache_resp_data, 320 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 321 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 322 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 323 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 324 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 325 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 326 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 327 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 328 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 329 )) 330 331 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 332 exceptionVec(loadAccessFault) := isLr 333 exceptionVec(storeAccessFault) := !isLr 334 assert(!exceptionVec(loadAccessFault)) 335 assert(!exceptionVec(storeAccessFault)) 336 } 337 338 resp_data := resp_data_wire 339 state := s_finish 340 out_valid := true.B 341 } 342 343 io.out.valid := out_valid 344 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 345 io.out.bits := DontCare 346 io.out.bits.uop := in.uop 347 io.out.bits.uop.cf.exceptionVec := exceptionVec 348 io.out.bits.data := resp_data 349 io.out.bits.redirectValid := false.B 350 io.out.bits.debug.isMMIO := is_mmio 351 io.out.bits.debug.paddr := paddr 352 when (io.out.fire) { 353 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 354 state := s_invalid 355 out_valid := false.B 356 } 357 358 when (state === s_finish) { 359 data_valid := false.B 360 } 361 362 when (io.redirect.valid) { 363 atom_override_xtval := false.B 364 } 365 366 // atomic trigger 367 val csrCtrl = io.csrCtrl 368 val tdata = Reg(Vec(6, new MatchTriggerIO)) 369 val tEnable = RegInit(VecInit(Seq.fill(6)(false.B))) 370 val en = csrCtrl.trigger_enable 371 tEnable := VecInit(en(2), en (3), en(7), en(4), en(5), en(9)) 372 when(csrCtrl.mem_trigger.t.valid) { 373 tdata(csrCtrl.mem_trigger.t.bits.addr) := csrCtrl.mem_trigger.t.bits.tdata 374 } 375 val lTriggerMapping = Map(0 -> 2, 1 -> 3, 2 -> 5) 376 val sTriggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 4) 377 378 val backendTriggerHitReg = Reg(Vec(6, Bool())) 379 backendTriggerHitReg := VecInit(Seq.fill(6)(false.B)) 380 381 when(state === s_cache_req){ 382 // store trigger 383 val store_hit = Wire(Vec(3, Bool())) 384 for (j <- 0 until 3) { 385 store_hit(j) := !tdata(sTriggerMapping(j)).select && TriggerCmp( 386 vaddr, 387 tdata(sTriggerMapping(j)).tdata2, 388 tdata(sTriggerMapping(j)).matchType, 389 tEnable(sTriggerMapping(j)) 390 ) 391 backendTriggerHitReg(sTriggerMapping(j)) := store_hit(j) 392 } 393 394 when(tdata(0).chain) { 395 backendTriggerHitReg(0) := store_hit(0) && store_hit(1) 396 backendTriggerHitReg(1) := store_hit(0) && store_hit(1) 397 } 398 399 when(!in.uop.cf.trigger.backendEn(0)) { 400 backendTriggerHitReg(4) := false.B 401 } 402 403 // load trigger 404 val load_hit = Wire(Vec(3, Bool())) 405 for (j <- 0 until 3) { 406 407 val addrHit = TriggerCmp( 408 vaddr, 409 tdata(lTriggerMapping(j)).tdata2, 410 tdata(lTriggerMapping(j)).matchType, 411 tEnable(lTriggerMapping(j)) 412 ) 413 load_hit(j) := addrHit && !tdata(lTriggerMapping(j)).select 414 backendTriggerHitReg(lTriggerMapping(j)) := load_hit(j) 415 } 416 when(tdata(2).chain) { 417 backendTriggerHitReg(2) := load_hit(0) && load_hit(1) 418 backendTriggerHitReg(3) := load_hit(0) && load_hit(1) 419 } 420 when(!in.uop.cf.trigger.backendEn(1)) { 421 backendTriggerHitReg(5) := false.B 422 } 423 } 424 425 // addr trigger do cmp at s_cache_req 426 // trigger result is used at s_finish 427 // thus we can delay it safely 428 io.out.bits.uop.cf.trigger.backendHit := VecInit(Seq.fill(6)(false.B)) 429 when(isLr){ 430 // enable load trigger 431 io.out.bits.uop.cf.trigger.backendHit(2) := backendTriggerHitReg(2) 432 io.out.bits.uop.cf.trigger.backendHit(3) := backendTriggerHitReg(3) 433 io.out.bits.uop.cf.trigger.backendHit(5) := backendTriggerHitReg(5) 434 }.otherwise{ 435 // enable store trigger 436 io.out.bits.uop.cf.trigger.backendHit(0) := backendTriggerHitReg(0) 437 io.out.bits.uop.cf.trigger.backendHit(1) := backendTriggerHitReg(1) 438 io.out.bits.uop.cf.trigger.backendHit(4) := backendTriggerHitReg(4) 439 } 440 441 if (env.EnableDifftest) { 442 val difftest = Module(new DifftestAtomicEvent) 443 difftest.io.clock := clock 444 difftest.io.coreid := io.hartId 445 difftest.io.atomicResp := state === s_cache_resp_latch 446 difftest.io.atomicAddr := paddr_reg 447 difftest.io.atomicData := data_reg 448 difftest.io.atomicMask := mask_reg 449 difftest.io.atomicFuop := fuop_reg 450 difftest.io.atomicOut := resp_data_wire 451 } 452 453 if (env.EnableDifftest || env.AlwaysBasicDiff) { 454 val uop = io.out.bits.uop 455 val difftest = Module(new DifftestLrScEvent) 456 difftest.io.clock := clock 457 difftest.io.coreid := io.hartId 458 difftest.io.valid := io.out.fire && 459 (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w) 460 difftest.io.success := is_lrsc_valid 461 } 462} 463