1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import xiangshan._ 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig.WbConfig 10import xiangshan.backend.decode.{ImmUnion, XDecode} 11import xiangshan.backend.exu.ExeUnitParams 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 14import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 15import xiangshan.backend.rob.RobPtr 16import xiangshan.frontend._ 17import xiangshan.mem.{LqPtr, SqPtr} 18 19object Bundles { 20 21 // frontend -> backend 22 class StaticInst(implicit p: Parameters) extends XSBundle { 23 val instr = UInt(32.W) 24 val pc = UInt(VAddrBits.W) 25 val foldpc = UInt(MemPredPCWidth.W) 26 val exceptionVec = ExceptionVec() 27 val trigger = new TriggerCf 28 val preDecodeInfo = new PreDecodeInfo 29 val pred_taken = Bool() 30 val crossPageIPFFix = Bool() 31 val ftqPtr = new FtqPtr 32 val ftqOffset = UInt(log2Up(PredictWidth).W) 33 34 def connectCtrlFlow(source: CtrlFlow): Unit = { 35 this.instr := source.instr 36 this.pc := source.pc 37 this.foldpc := source.foldpc 38 this.exceptionVec := source.exceptionVec 39 this.trigger := source.trigger 40 this.preDecodeInfo := source.pd 41 this.pred_taken := source.pred_taken 42 this.crossPageIPFFix := source.crossPageIPFFix 43 this.ftqPtr := source.ftqPtr 44 this.ftqOffset := source.ftqOffset 45 } 46 } 47 48 // StaticInst --[Decode]--> DecodedInst 49 class DecodedInst(implicit p: Parameters) extends XSBundle { 50 def numPSrc = 5 51 def numLSrc = 3 52 // passed from StaticInst 53 val instr = UInt(32.W) 54 val pc = UInt(VAddrBits.W) 55 val foldpc = UInt(MemPredPCWidth.W) 56 val exceptionVec = ExceptionVec() 57 val trigger = new TriggerCf 58 val preDecodeInfo = new PreDecodeInfo 59 val pred_taken = Bool() 60 val crossPageIPFFix = Bool() 61 val ftqPtr = new FtqPtr 62 val ftqOffset = UInt(log2Up(PredictWidth).W) 63 // decoded 64 val srcType = Vec(numLSrc, SrcType()) 65 val lsrc = Vec(numLSrc, UInt(6.W)) 66 val ldest = UInt(6.W) 67 val fuType = FuType() 68 val fuOpType = FuOpType() 69 val rfWen = Bool() 70 val fpWen = Bool() 71 val vecWen = Bool() 72 val isXSTrap = Bool() 73 val waitForward = Bool() // no speculate execution 74 val blockBackward = Bool() 75 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 76 val selImm = SelImm() 77 val imm = UInt(ImmUnion.maxLen.W) 78 val fpu = new FPUCtrlSignals 79 val vpu = new VPUCtrlSignals 80 val isMove = Bool() 81 val uopIdx = UInt(5.W) 82 // val vconfig = UInt(16.W) 83 val isVset = Bool() 84 val commitType = CommitType() // Todo: remove it 85 86 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 87 isXSTrap, waitForward, blockBackward, flushPipe, selImm) 88 89 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 90 val decoder: Seq[UInt] = ListLookup( 91 inst, XDecode.decodeDefault.map(bitPatToUInt), 92 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 93 ) 94 allSignals zip decoder foreach { case (s, d) => s := d } 95 this 96 } 97 98 def isSoftPrefetch: Bool = { 99 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 100 } 101 102 def connectStaticInst(source: StaticInst): Unit = { 103 for ((name, data) <- this.elements) { 104 if (source.elements.contains(name)) { 105 data := source.elements(name) 106 } 107 } 108 } 109 } 110 111 // DecodedInst --[Rename]--> DynInst 112 class DynInst(implicit p: Parameters) extends XSBundle { 113 def numLSrc = 3 114 // vector inst need vs1, vs2, vd, v0, vl&vtype, 5 psrcs 115 def numPSrc = 5 116 // passed from StaticInst 117 val instr = UInt(32.W) 118 val pc = UInt(VAddrBits.W) 119 val foldpc = UInt(MemPredPCWidth.W) 120 val exceptionVec = ExceptionVec() 121 val trigger = new TriggerCf 122 val preDecodeInfo = new PreDecodeInfo 123 val pred_taken = Bool() 124 val crossPageIPFFix = Bool() 125 val ftqPtr = new FtqPtr 126 val ftqOffset = UInt(log2Up(PredictWidth).W) 127 // passed from DecodedInst 128 val srcType = Vec(numLSrc, SrcType()) 129 val lsrc = Vec(numLSrc, UInt(6.W)) 130 val ldest = UInt(6.W) 131 val fuType = FuType() 132 val fuOpType = FuOpType() 133 val rfWen = Bool() 134 val fpWen = Bool() 135 val vecWen = Bool() 136 val isXSTrap = Bool() 137 val waitForward = Bool() // no speculate execution 138 val blockBackward = Bool() 139 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 140 val selImm = SelImm() 141 val imm = UInt(XLEN.W) // Todo: check if it need minimized 142 val fpu = new FPUCtrlSignals 143 val vpu = new VPUCtrlSignals 144 val isMove = Bool() 145 val uopIdx = UInt(5.W) 146 // val vconfig = UInt(16.W) 147 val isVset = Bool() 148 val commitType = CommitType() 149 // rename 150 val srcState = Vec(numPSrc, SrcState()) 151 val psrc = Vec(numPSrc, UInt(PhyRegIdxWidth.W)) 152 val pdest = UInt(PhyRegIdxWidth.W) 153 val oldPdest = UInt(PhyRegIdxWidth.W) 154 val robIdx = new RobPtr 155 156 val eliminatedMove = Bool() 157 val debugInfo = new PerfDebugInfo 158 val storeSetHit = Bool() // inst has been allocated an store set 159 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 160 // Load wait is needed 161 // load inst will not be executed until former store (predicted by mdp) addr calcuated 162 val loadWaitBit = Bool() 163 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 164 // load inst will not be executed until ALL former store addr calcuated 165 val loadWaitStrict = Bool() 166 val ssid = UInt(SSIDWidth.W) 167 // Todo 168 val lqIdx = new LqPtr 169 val sqIdx = new SqPtr 170 // debug module 171 val singleStep = Bool() 172 // schedule 173 val replayInst = Bool() 174 175 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 176 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 177 178 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 179 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 180 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 181 182 def srcIsReady: Vec[Bool] = { 183 VecInit(this.srcType.zip(this.srcState).map { 184 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 185 }) 186 } 187 188 def clearExceptions( 189 exceptionBits: Seq[Int] = Seq(), 190 flushPipe : Boolean = false, 191 replayInst : Boolean = false 192 ): DynInst = { 193 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 194 if (!flushPipe) { this.flushPipe := false.B } 195 if (!replayInst) { this.replayInst := false.B } 196 this 197 } 198 199 def asWakeUpBundle: IssueQueueWakeUpBundle = { 200 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 201 wakeup.rfWen := this.rfWen 202 wakeup.fpWen := this.fpWen 203 wakeup.vecWen := this.vecWen 204 wakeup.pdest := this.pdest 205 wakeup 206 } 207 } 208 209 trait BundleSource { 210 var source = "not exist" 211 } 212 213 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 214 val rfWen = Bool() 215 val fpWen = Bool() 216 val vecWen = Bool() 217 val pdest = UInt(PregIdxWidth.W) 218 219 /** 220 * @param successor Seq[(psrc, srcType)] 221 * @return Seq[if wakeup psrc] 222 */ 223 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 224 successor.map { case (thatPsrc, srcType) => 225 val pdestMatch = pdest === thatPsrc 226 pdestMatch && ( 227 SrcType.isFp(srcType) && this.fpWen || 228 SrcType.isXp(srcType) && this.rfWen || 229 SrcType.isVp(srcType) && this.vecWen 230 ) && valid 231 } 232 } 233 } 234 235 object VsewBundle { 236 def apply() = UInt(2.W) // 8/16/32/64 --> 0/1/2/3 237 } 238 239 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 240 val vlmul = SInt(3.W) // 1/8~8 --> -3~3 241 val vsew = VsewBundle() 242 val vta = Bool() // 1: agnostic, 0: undisturbed 243 val vma = Bool() // 1: agnostic, 0: undisturbed 244 val vm = Bool() // 0: need v0.t 245 val vill = Bool() 246 // vector load/store 247 val nf = UInt(3.W) 248 val lsumop = UInt(5.W) // lumop or sumop 249 // used for vector index load/store and vrgatherei16.vv 250 val idxEmul = UInt(3.W) 251 } 252 253 // DynInst --[IssueQueue]--> DataPath 254 class IssueQueueIssueBundle( 255 iqParams: IssueBlockParams, 256 exuParams: ExeUnitParams, 257 addrWidth: Int, 258 vaddrBits: Int 259 )(implicit 260 p: Parameters 261 ) extends Bundle { 262 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 263 264 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 265 rfReadDataCfgSet.map((set: Set[DataConfig]) => 266 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 267 ) 268 )) 269 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 270 val immType = SelImm() // used to select imm extractor 271 val common = new ExuInput(exuParams) 272 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 273 val addrOH = UInt(iqParams.numEntries.W) 274 275 def getSource: SchedulerType = exuParams.getWBSource 276 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 277 def getFpRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readFp) 278 } 279 280 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 281 val og0resp = Valid(new StatusArrayDeqRespBundle) 282 val og1resp = Valid(new StatusArrayDeqRespBundle) 283 } 284 285 // DataPath --[ExuInput]--> Exu 286 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 287 val fuType = FuType() 288 val fuOpType = FuOpType() 289 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 290 val imm = UInt(XLEN.W) 291 val robIdx = new RobPtr 292 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 293 val isFirstIssue = Bool() // Only used by store yet 294 val pdest = UInt(params.wbPregIdxWidth.W) 295 val rfWen = if (params.writeIntRf) Some(Bool()) else None 296 val fpWen = if (params.writeFpRf) Some(Bool()) else None 297 val vecWen = if (params.writeVecRf) Some(Bool()) else None 298 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 299 val flushPipe = if (params.flushPipe) Some(Bool()) else None 300 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 301 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 302 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 303 val ftqIdx = if (params.needPc || params.replayInst) 304 Some(new FtqPtr) else None 305 val ftqOffset = if (params.needPc || params.replayInst) 306 Some(UInt(log2Up(PredictWidth).W)) else None 307 val predictInfo = if (params.hasPredecode) Some(new Bundle { 308 val target = UInt(VAddrData().dataWidth.W) 309 val taken = Bool() 310 }) else None 311 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 312 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 313 314 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 315 // src is assigned to rfReadData 316 this.fuType := source.common.fuType 317 this.fuOpType := source.common.fuOpType 318 this.imm := source.common.imm 319 this.robIdx := source.common.robIdx 320 this.pdest := source.common.pdest 321 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 322 this.iqIdx := source.common.iqIdx // Only used by mem feedback 323 this.rfWen .foreach(_ := source.common.rfWen.get) 324 this.fpWen .foreach(_ := source.common.fpWen.get) 325 this.vecWen .foreach(_ := source.common.vecWen.get) 326 this.fpu .foreach(_ := source.common.fpu.get) 327 this.flushPipe .foreach(_ := source.common.flushPipe.get) 328 this.pc .foreach(_ := source.jmp.get.pc) 329 this.jalrTarget .foreach(_ := source.jmp.get.target) 330 this.preDecode .foreach(_ := source.common.preDecode.get) 331 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 332 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 333 this.predictInfo .foreach(_ := source.common.predictInfo.get) 334 this.lqIdx .foreach(_ := source.common.lqIdx.get) 335 this.sqIdx .foreach(_ := source.common.sqIdx.get) 336 } 337 } 338 339 // ExuInput --[FuncUnit]--> ExuOutput 340 class ExuOutput( 341 val params: ExeUnitParams, 342 )(implicit 343 val p: Parameters 344 ) extends Bundle with BundleSource with HasXSParameter { 345 val data = UInt(params.dataBitsMax.W) 346 val pdest = UInt(params.wbPregIdxWidth.W) 347 val robIdx = new RobPtr 348 val intWen = if (params.writeIntRf) Some(Bool()) else None 349 val fpWen = if (params.writeFpRf) Some(Bool()) else None 350 val vecWen = if (params.writeVecRf) Some(Bool()) else None 351 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 352 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 353 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 354 val flushPipe = if (params.flushPipe) Some(Bool()) else None 355 val replay = if (params.replayInst) Some(Bool()) else None 356 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 357 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 358 Some(new SqPtr()) else None 359 val ftqIdx = if (params.needPc || params.replayInst) 360 Some(new FtqPtr) else None 361 val ftqOffset = if (params.needPc || params.replayInst) 362 Some(UInt(log2Up(PredictWidth).W)) else None 363 // uop info 364 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 365 val debug = new DebugBundle 366 val debugInfo = new PerfDebugInfo 367 } 368 369 // ExuOutput + DynInst --> WriteBackBundle 370 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 371 val rfWen = Bool() 372 val fpWen = Bool() 373 val vecWen = Bool() 374 val pdest = UInt(params.pregIdxWidth.W) 375 val data = UInt(params.dataWidth.W) 376 val robIdx = new RobPtr()(p) 377 val flushPipe = Bool() 378 val replayInst = Bool() 379 val redirect = ValidIO(new Redirect) 380 val fflags = UInt(5.W) 381 val exceptionVec = ExceptionVec() 382 val debug = new DebugBundle 383 val debugInfo = new PerfDebugInfo 384 385 def fromExuOutput(source: ExuOutput) = { 386 this.rfWen := source.intWen.getOrElse(false.B) 387 this.fpWen := source.fpWen.getOrElse(false.B) 388 this.vecWen := source.vecWen.getOrElse(false.B) 389 this.pdest := source.pdest 390 this.data := source.data 391 this.robIdx := source.robIdx 392 this.flushPipe := source.flushPipe.getOrElse(false.B) 393 this.replayInst := source.replay.getOrElse(false.B) 394 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 395 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 396 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 397 this.debug := source.debug 398 this.debugInfo := source.debugInfo 399 } 400 401 def asWakeUpBundle: IssueQueueWakeUpBundle = { 402 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 403 wakeup.rfWen := this.rfWen 404 wakeup.fpWen := this.fpWen 405 wakeup.vecWen := this.vecWen 406 wakeup.pdest := this.pdest 407 wakeup.source = this.source 408 wakeup 409 } 410 411 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 412 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 413 rfWrite.wen := this.rfWen && fire 414 rfWrite.addr := this.pdest 415 rfWrite.data := this.data 416 rfWrite.intWen := this.rfWen 417 rfWrite.fpWen := false.B 418 rfWrite.vecWen := false.B 419 rfWrite 420 } 421 422 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 423 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 424 rfWrite.wen := (this.fpWen || this.vecWen) && fire 425 rfWrite.addr := this.pdest 426 rfWrite.data := this.data 427 rfWrite.intWen := false.B 428 rfWrite.fpWen := this.fpWen 429 rfWrite.vecWen := this.vecWen 430 rfWrite 431 } 432 } 433 434 class ExceptionInfo extends Bundle { 435 val pc = UInt(VAddrData().dataWidth.W) 436 val instr = UInt(32.W) 437 val commitType = CommitType() 438 val exceptionVec = ExceptionVec() 439 val singleStep = Bool() 440 val crossPageIPFFix = Bool() 441 val isInterrupt = Bool() 442 } 443 444 class MemExuInput(implicit p: Parameters) extends XSBundle { 445 val uop = new DynInst 446 val src = Vec(3, UInt(XLEN.W)) 447 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 448 val isFirstIssue = Bool() 449 } 450 451 class MemExuOutput(implicit p: Parameters) extends XSBundle { 452 val uop = new DynInst 453 val data = UInt(XLEN.W) 454 val debug = new DebugBundle 455 } 456 457 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 458 val uop = new DynInst 459 val flag = UInt(1.W) 460 } 461} 462