xref: /XiangShan/src/main/scala/xiangshan/DbEntry.scala (revision da3bf434d2eaa53cd07e3992eb63aefb88a6f0da) 
1package xiangshan
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util.log2Ceil
6import xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo}
7import xiangshan.cache.DCacheBundle
8
9/** Mem */
10class LoadMissEntry(implicit p: Parameters) extends DCacheBundle {
11  val timeCnt = UInt(XLEN.W)
12  val robIdx = UInt(log2Ceil(RobSize).W)
13  val paddr = UInt(PAddrBits.W)
14  val vaddr = UInt(VAddrBits.W)
15  // 1:first hit, 2:first miss, 3:second miss
16  val missState = UInt(3.W)
17}
18
19class InstInfoEntry(implicit p: Parameters) extends XSBundle{
20  val globalID = UInt(XLEN.W)
21  val robIdx = UInt(log2Ceil(RobSize).W)
22  val instType = FuType()
23  val exceptType = UInt(ExceptionVec.ExceptionVecSize.W)
24  val ivaddr = UInt(VAddrBits.W)
25  val dvaddr = UInt(VAddrBits.W) // the l/s access address
26  val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid
27  val tlbLatency = UInt(XLEN.W)  // original requirements is L1toL2TlbLatency
28  val accessLatency = UInt(XLEN.W)  // RS out time --> write back time
29  val executeLatency = UInt(XLEN.W)
30  val issueLatency = UInt(XLEN.W)
31  val lsInfo = new DebugLsInfo
32  val mdpInfo = new DebugMdpInfo
33  val issueTime = UInt(XLEN.W)
34  val writebackTime = UInt(XLEN.W)
35}