xref: /XiangShan/src/main/scala/xiangshan/DbEntry.scala (revision 248b9a04893bb9d411c7dff38e57b4ef6c6dd3fd) 
1package xiangshan
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util.log2Ceil
6import xiangshan.backend.ctrlblock.{DebugLsInfo, DebugMdpInfo}
7import xiangshan.cache.{DCacheBundle, HasDCacheParameters}
8import xiangshan.backend.fu.FuType
9import utility.MemReqSource
10import xiangshan.mem.prefetch.HasL1PrefetchHelper
11
12/** Mem */
13class LoadMissEntry(implicit p: Parameters) extends DCacheBundle {
14  val timeCnt = UInt(XLEN.W)
15  val robIdx = UInt(log2Ceil(RobSize).W)
16  val paddr = UInt(PAddrBits.W)
17  val vaddr = UInt(VAddrBits.W)
18  // 1:first hit, 2:first miss, 3:second miss
19  val missState = UInt(3.W)
20}
21
22class LoadAccessEntry(implicit p: Parameters) extends LoadMissEntry{
23  val pred_way_num = UInt(XLEN.W)
24  val dm_way_num = UInt(XLEN.W)
25  val real_way_num = UInt(XLEN.W)
26}
27
28class InstInfoEntry(implicit p: Parameters) extends XSBundle{
29  /*
30   * The annotated signals are discarded in New Backend.
31   * But it can be used as a signal reference for instinfo
32   */
33  val robIdx = UInt(log2Ceil(RobSize).W)
34  // val globalID = UInt(XLEN.W)
35  // val instType = FuType()
36  // val mdpInfo = new DebugMdpInfo
37  // val ivaddr = UInt(VAddrBits.W)
38  val dvaddr = UInt(VAddrBits.W) // the l/s access address
39  val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid
40  val issueTime = UInt(XLEN.W)
41  val writebackTime = UInt(XLEN.W)
42  val dispatchLatency = UInt(XLEN.W)
43  val enqRsLatency = UInt(XLEN.W)
44  val selectLatency = UInt(XLEN.W)
45  val issueLatency = UInt(XLEN.W)
46  val executeLatency = UInt(XLEN.W)
47  val rsFuLatency = UInt(XLEN.W)
48  // val commitLatency = UInt(XLEN.W) // can not record when writing back
49  val tlbLatency = UInt(XLEN.W)  // original requirements is L1toL2TlbLatency
50  val lsInfo = new DebugLsInfo
51  val exceptType = UInt(ExceptionVec.ExceptionVecSize.W)
52}
53
54class LoadInfoEntry(implicit p: Parameters) extends XSBundle{
55  val pc = UInt(VAddrBits.W)
56  val vaddr = UInt(VAddrBits.W)
57  val paddr = UInt(PAddrBits.W)
58  val cacheMiss = Bool()
59  val tlbQueryLatency = UInt(64.W)
60  val exeLatency = UInt(64.W)
61}
62
63class StreamPFTraceInEntry(implicit p: Parameters) extends XSBundle with HasL1PrefetchHelper{
64  val TriggerPC = UInt(VAddrBits.W)
65  val TriggerVaddr = UInt(VAddrBits.W)
66  val PFVaddr = UInt(VAddrBits.W)
67  val PFSink = UInt(SINK_BITS.W)
68}
69
70class StreamTrainTraceEntry(implicit p: Parameters) extends XSBundle with HasDCacheParameters{
71  val Type = UInt(MemReqSource.reqSourceBits.W)
72  val OldAddr = UInt(VAddrBits.W)
73  val CurAddr = UInt(VAddrBits.W)
74  val Offset = UInt(32.W)
75  val Score = UInt(32.W)
76  val Miss = Bool()
77}
78
79class StreamPFTraceOutEntry(implicit p: Parameters) extends XSBundle with HasL1PrefetchHelper{
80  val PFVaddr = UInt(VAddrBits.W)
81  val PFSink = UInt(SINK_BITS.W)
82}