1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, HasDCacheParameters, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30import xiangshan.v2backend.Bundles.{MemExuInput, MemExuOutput} 31 32class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants with HasDCacheParameters{ 33 val io = IO(new Bundle() { 34 val hartId = Input(UInt(8.W)) 35 val in = Flipped(Decoupled(new MemExuInput)) 36 val storeDataIn = Flipped(Valid(new MemExuOutput)) // src2 from rs 37 val out = Decoupled(new MemExuOutput) 38 val dcache = new AtomicWordIO 39 val dtlb = new TlbRequestIO(2) 40 val pmpResp = Flipped(new PMPRespBundle()) 41 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 42 val flush_sbuffer = new SbufferFlushBundle 43 val feedbackSlow = ValidIO(new RSFeedback) 44 val redirect = Flipped(ValidIO(new Redirect)) 45 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 46 val csrCtrl = Flipped(new CustomCSRCtrlIO) 47 }) 48 49 //------------------------------------------------------- 50 // Atomics Memory Accsess FSM 51 //------------------------------------------------------- 52 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 53 val state = RegInit(s_invalid) 54 val out_valid = RegInit(false.B) 55 val data_valid = RegInit(false.B) 56 val in = Reg(new MemExuInput()) 57 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 58 val atom_override_xtval = RegInit(false.B) 59 val isLr = in.uop.fuOpType === LSUOpType.lr_w || in.uop.fuOpType === LSUOpType.lr_d 60 // paddr after translation 61 val paddr = Reg(UInt()) 62 val vaddr = in.src(0) 63 val is_mmio = Reg(Bool()) 64 // pmp check 65 val static_pm = Reg(Valid(Bool())) // valid for static, bits for mmio 66 // dcache response data 67 val resp_data = Reg(UInt()) 68 val resp_data_wire = WireInit(0.U) 69 val is_lrsc_valid = Reg(Bool()) 70 // sbuffer is empty or not 71 val sbuffer_empty = io.flush_sbuffer.empty 72 73 74 // Difftest signals 75 val paddr_reg = Reg(UInt(64.W)) 76 val data_reg = Reg(UInt(64.W)) 77 val mask_reg = Reg(UInt(8.W)) 78 val fuop_reg = Reg(UInt(8.W)) 79 80 io.exceptionAddr.valid := atom_override_xtval 81 io.exceptionAddr.bits := in.src(0) 82 83 // assign default value to output signals 84 io.in.ready := false.B 85 86 io.dcache.req.valid := false.B 87 io.dcache.req.bits := DontCare 88 89 io.dtlb.req.valid := false.B 90 io.dtlb.req.bits := DontCare 91 io.dtlb.req_kill := false.B 92 io.dtlb.resp.ready := true.B 93 94 io.flush_sbuffer.valid := false.B 95 96 XSDebug("state: %d\n", state) 97 98 when (state === s_invalid) { 99 io.in.ready := true.B 100 when (io.in.fire) { 101 in := io.in.bits 102 in.src(1) := in.src(1) // leave src2 unchanged 103 state := s_tlb_and_flush_sbuffer_req 104 } 105 } 106 107 when (io.storeDataIn.fire) { 108 in.src(1) := io.storeDataIn.bits.data 109 data_valid := true.B 110 } 111 112 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 113 114 // Send TLB feedback to store issue queue 115 // we send feedback right after we receives request 116 // also, we always treat amo as tlb hit 117 // since we will continue polling tlb all by ourself 118 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 119 io.feedbackSlow.bits.hit := true.B 120 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 121 io.feedbackSlow.bits.flushState := DontCare 122 io.feedbackSlow.bits.sourceType := DontCare 123 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 124 125 // tlb translation, manipulating signals && deal with exception 126 // at the same time, flush sbuffer 127 when (state === s_tlb_and_flush_sbuffer_req) { 128 // send req to dtlb 129 // keep firing until tlb hit 130 io.dtlb.req.valid := true.B 131 io.dtlb.req.bits.vaddr := in.src(0) 132 io.dtlb.resp.ready := true.B 133 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 134 io.dtlb.req.bits.debug.pc := in.uop.pc 135 io.dtlb.req.bits.debug.isFirstIssue := false.B 136 137 // send req to sbuffer to flush it if it is not empty 138 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 139 140 when(io.dtlb.resp.fire){ 141 paddr := io.dtlb.resp.bits.paddr(0) 142 // exception handling 143 val addrAligned = LookupTree(in.uop.fuOpType(1,0), List( 144 "b00".U -> true.B, //b 145 "b01".U -> (in.src(0)(0) === 0.U), //h 146 "b10".U -> (in.src(0)(1,0) === 0.U), //w 147 "b11".U -> (in.src(0)(2,0) === 0.U) //d 148 )) 149 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 150 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 151 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 152 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 153 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 154 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 155 static_pm := io.dtlb.resp.bits.static_pm 156 157 when (!io.dtlb.resp.bits.miss) { 158 when (!addrAligned) { 159 // NOTE: when addrAligned, do not need to wait tlb actually 160 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 161 // if there are exceptions, no need to execute it 162 state := s_finish 163 out_valid := true.B 164 atom_override_xtval := true.B 165 } .otherwise { 166 state := s_pm 167 } 168 } 169 } 170 } 171 172 when (state === s_pm) { 173 val pmp = WireInit(io.pmpResp) 174 when (static_pm.valid) { 175 pmp.ld := false.B 176 pmp.st := false.B 177 pmp.instr := false.B 178 pmp.mmio := static_pm.bits 179 } 180 is_mmio := pmp.mmio 181 // NOTE: only handle load/store exception here, if other exception happens, don't send here 182 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 183 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 184 val exception_pa = pmp.st || pmp.ld 185 when (exception_va || exception_pa) { 186 state := s_finish 187 out_valid := true.B 188 atom_override_xtval := true.B 189 }.otherwise { 190 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 191 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 192 } 193 // update storeAccessFault bit 194 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || pmp.ld && isLr 195 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || pmp.ld && !isLr 196 } 197 198 when (state === s_wait_flush_sbuffer_resp) { 199 when (sbuffer_empty) { 200 state := s_cache_req 201 } 202 } 203 204 when (state === s_cache_req) { 205 val pipe_req = io.dcache.req.bits 206 pipe_req := DontCare 207 208 pipe_req.cmd := LookupTree(in.uop.fuOpType, List( 209 LSUOpType.lr_w -> M_XLR, 210 LSUOpType.sc_w -> M_XSC, 211 LSUOpType.amoswap_w -> M_XA_SWAP, 212 LSUOpType.amoadd_w -> M_XA_ADD, 213 LSUOpType.amoxor_w -> M_XA_XOR, 214 LSUOpType.amoand_w -> M_XA_AND, 215 LSUOpType.amoor_w -> M_XA_OR, 216 LSUOpType.amomin_w -> M_XA_MIN, 217 LSUOpType.amomax_w -> M_XA_MAX, 218 LSUOpType.amominu_w -> M_XA_MINU, 219 LSUOpType.amomaxu_w -> M_XA_MAXU, 220 221 LSUOpType.lr_d -> M_XLR, 222 LSUOpType.sc_d -> M_XSC, 223 LSUOpType.amoswap_d -> M_XA_SWAP, 224 LSUOpType.amoadd_d -> M_XA_ADD, 225 LSUOpType.amoxor_d -> M_XA_XOR, 226 LSUOpType.amoand_d -> M_XA_AND, 227 LSUOpType.amoor_d -> M_XA_OR, 228 LSUOpType.amomin_d -> M_XA_MIN, 229 LSUOpType.amomax_d -> M_XA_MAX, 230 LSUOpType.amominu_d -> M_XA_MINU, 231 LSUOpType.amomaxu_d -> M_XA_MAXU 232 )) 233 pipe_req.miss := false.B 234 pipe_req.probe := false.B 235 pipe_req.probe_need_data := false.B 236 pipe_req.source := AMO_SOURCE.U 237 pipe_req.addr := get_block_addr(paddr) 238 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 239 pipe_req.word_idx := get_word(paddr) 240 pipe_req.amo_data := genWdata(in.src(1), in.uop.fuOpType(1,0)) 241 pipe_req.amo_mask := genWmask(paddr, in.uop.fuOpType(1,0)) 242 243 io.dcache.req.valid := Mux( 244 io.dcache.req.bits.cmd === M_XLR, 245 !io.dcache.block_lr, // block lr to survive in lr storm 246 data_valid // wait until src(1) is ready 247 ) 248 249 when(io.dcache.req.fire){ 250 state := s_cache_resp 251 paddr_reg := paddr 252 data_reg := io.dcache.req.bits.amo_data 253 mask_reg := io.dcache.req.bits.amo_mask 254 fuop_reg := in.uop.fuOpType 255 } 256 } 257 258 val dcache_resp_data = Reg(UInt()) 259 val dcache_resp_id = Reg(UInt()) 260 val dcache_resp_error = Reg(Bool()) 261 262 when (state === s_cache_resp) { 263 // when not miss 264 // everything is OK, simply send response back to sbuffer 265 // when miss and not replay 266 // wait for missQueue to handling miss and replaying our request 267 // when miss and replay 268 // req missed and fail to enter missQueue, manually replay it later 269 // TODO: add assertions: 270 // 1. add a replay delay counter? 271 // 2. when req gets into MissQueue, it should not miss any more 272 when(io.dcache.resp.fire()) { 273 when(io.dcache.resp.bits.miss) { 274 when(io.dcache.resp.bits.replay) { 275 state := s_cache_req 276 } 277 } .otherwise { 278 dcache_resp_data := io.dcache.resp.bits.data 279 dcache_resp_id := io.dcache.resp.bits.id 280 dcache_resp_error := io.dcache.resp.bits.error 281 state := s_cache_resp_latch 282 } 283 } 284 } 285 286 when (state === s_cache_resp_latch) { 287 is_lrsc_valid := dcache_resp_id 288 val rdataSel = LookupTree(paddr(2, 0), List( 289 "b000".U -> dcache_resp_data(63, 0), 290 "b001".U -> dcache_resp_data(63, 8), 291 "b010".U -> dcache_resp_data(63, 16), 292 "b011".U -> dcache_resp_data(63, 24), 293 "b100".U -> dcache_resp_data(63, 32), 294 "b101".U -> dcache_resp_data(63, 40), 295 "b110".U -> dcache_resp_data(63, 48), 296 "b111".U -> dcache_resp_data(63, 56) 297 )) 298 299 resp_data_wire := LookupTree(in.uop.fuOpType, List( 300 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 301 LSUOpType.sc_w -> dcache_resp_data, 302 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 303 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 304 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 305 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 306 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 307 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 308 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 309 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 310 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 311 312 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 313 LSUOpType.sc_d -> dcache_resp_data, 314 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 315 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 316 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 317 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 318 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 319 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 320 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 321 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 322 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 323 )) 324 325 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 326 exceptionVec(loadAccessFault) := isLr 327 exceptionVec(storeAccessFault) := !isLr 328 assert(!exceptionVec(loadAccessFault)) 329 assert(!exceptionVec(storeAccessFault)) 330 } 331 332 resp_data := resp_data_wire 333 state := s_finish 334 out_valid := true.B 335 } 336 337 io.out.valid := out_valid 338 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 339 io.out.bits := DontCare 340 io.out.bits.uop := in.uop 341 io.out.bits.uop.exceptionVec := exceptionVec 342 io.out.bits.data := resp_data 343 io.out.bits.debug.isMMIO := is_mmio 344 io.out.bits.debug.paddr := paddr 345 when (io.out.fire) { 346 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.pc, io.dcache.resp.bits.data) 347 state := s_invalid 348 out_valid := false.B 349 } 350 351 when (state === s_finish) { 352 data_valid := false.B 353 } 354 355 when (io.redirect.valid) { 356 atom_override_xtval := false.B 357 } 358 359 // atomic trigger 360 val csrCtrl = io.csrCtrl 361 val tdata = Reg(Vec(6, new MatchTriggerIO)) 362 val tEnable = RegInit(VecInit(Seq.fill(6)(false.B))) 363 val en = csrCtrl.trigger_enable 364 tEnable := VecInit(en(2), en (3), en(7), en(4), en(5), en(9)) 365 when(csrCtrl.mem_trigger.t.valid) { 366 tdata(csrCtrl.mem_trigger.t.bits.addr) := csrCtrl.mem_trigger.t.bits.tdata 367 } 368 val lTriggerMapping = Map(0 -> 2, 1 -> 3, 2 -> 5) 369 val sTriggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 4) 370 371 val backendTriggerHitReg = Reg(Vec(6, Bool())) 372 backendTriggerHitReg := VecInit(Seq.fill(6)(false.B)) 373 374 when(state === s_cache_req){ 375 // store trigger 376 val store_hit = Wire(Vec(3, Bool())) 377 for (j <- 0 until 3) { 378 store_hit(j) := !tdata(sTriggerMapping(j)).select && TriggerCmp( 379 vaddr, 380 tdata(sTriggerMapping(j)).tdata2, 381 tdata(sTriggerMapping(j)).matchType, 382 tEnable(sTriggerMapping(j)) 383 ) 384 backendTriggerHitReg(sTriggerMapping(j)) := store_hit(j) 385 } 386 387 when(tdata(0).chain) { 388 backendTriggerHitReg(0) := store_hit(0) && store_hit(1) 389 backendTriggerHitReg(1) := store_hit(0) && store_hit(1) 390 } 391 392 when(!in.uop.trigger.backendEn(0)) { 393 backendTriggerHitReg(4) := false.B 394 } 395 396 // load trigger 397 val load_hit = Wire(Vec(3, Bool())) 398 for (j <- 0 until 3) { 399 400 val addrHit = TriggerCmp( 401 vaddr, 402 tdata(lTriggerMapping(j)).tdata2, 403 tdata(lTriggerMapping(j)).matchType, 404 tEnable(lTriggerMapping(j)) 405 ) 406 load_hit(j) := addrHit && !tdata(lTriggerMapping(j)).select 407 backendTriggerHitReg(lTriggerMapping(j)) := load_hit(j) 408 } 409 when(tdata(2).chain) { 410 backendTriggerHitReg(2) := load_hit(0) && load_hit(1) 411 backendTriggerHitReg(3) := load_hit(0) && load_hit(1) 412 } 413 when(!in.uop.trigger.backendEn(1)) { 414 backendTriggerHitReg(5) := false.B 415 } 416 } 417 418 // addr trigger do cmp at s_cache_req 419 // trigger result is used at s_finish 420 // thus we can delay it safely 421 io.out.bits.uop.trigger.backendHit := VecInit(Seq.fill(6)(false.B)) 422 when(isLr){ 423 // enable load trigger 424 io.out.bits.uop.trigger.backendHit(2) := backendTriggerHitReg(2) 425 io.out.bits.uop.trigger.backendHit(3) := backendTriggerHitReg(3) 426 io.out.bits.uop.trigger.backendHit(5) := backendTriggerHitReg(5) 427 }.otherwise{ 428 // enable store trigger 429 io.out.bits.uop.trigger.backendHit(0) := backendTriggerHitReg(0) 430 io.out.bits.uop.trigger.backendHit(1) := backendTriggerHitReg(1) 431 io.out.bits.uop.trigger.backendHit(4) := backendTriggerHitReg(4) 432 } 433 434 if (env.EnableDifftest) { 435 val difftest = Module(new DifftestAtomicEvent) 436 difftest.io.clock := clock 437 difftest.io.coreid := io.hartId 438 difftest.io.atomicResp := state === s_cache_resp_latch 439 difftest.io.atomicAddr := paddr_reg 440 difftest.io.atomicData := data_reg 441 difftest.io.atomicMask := mask_reg 442 difftest.io.atomicFuop := fuop_reg 443 difftest.io.atomicOut := resp_data_wire 444 } 445 446 if (env.EnableDifftest || env.AlwaysBasicDiff) { 447 val uop = io.out.bits.uop 448 val difftest = Module(new DifftestLrScEvent) 449 difftest.io.clock := clock 450 difftest.io.coreid := io.hartId 451 difftest.io.valid := io.out.fire && 452 (uop.fuOpType === LSUOpType.sc_d || uop.fuOpType === LSUOpType.sc_w) 453 difftest.io.success := is_lrsc_valid 454 } 455} 456