1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36 37class BaseConfig(n: Int) extends Config((site, here, up) => { 38 case XLen => 64 39 case DebugOptionsKey => DebugOptions() 40 case SoCParamsKey => SoCParameters() 41 case PMParameKey => PMParameters() 42 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 44 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 45 case JtagDTMKey => JtagDTMKey 46 case MaxHartIdBits => 2 47 case EnableJtag => true.B 48}) 49 50// Synthesizable minimal XiangShan 51// * It is still an out-of-order, super-scalaer arch 52// * L1 cache included 53// * L2 cache NOT included 54// * L3 cache included 55class MinimalConfig(n: Int = 1) extends Config( 56 new BaseConfig(n).alter((site, here, up) => { 57 case XSTileKey => up(XSTileKey).map( 58 _.copy( 59 DecodeWidth = 2, 60 RenameWidth = 2, 61 CommitWidth = 2, 62 FetchWidth = 4, 63 IssQueSize = 8, 64 NRPhyRegs = 64, 65 VirtualLoadQueueSize = 16, 66 LoadQueueRARSize = 16, 67 LoadQueueRAWSize = 12, 68 LoadQueueReplaySize = 8, 69 LoadUncacheBufferSize = 8, 70 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 71 RollbackGroupSize = 8, 72 StoreQueueSize = 12, 73 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 74 StoreQueueForwardWithMask = true, 75 RobSize = 32, 76 FtqSize = 8, 77 IBufSize = 16, 78 StoreBufferSize = 4, 79 StoreBufferThreshold = 3, 80 dpParams = DispatchParameters( 81 IntDqSize = 12, 82 FpDqSize = 12, 83 LsDqSize = 12, 84 IntDqDeqWidth = 4, 85 FpDqDeqWidth = 4, 86 LsDqDeqWidth = 4 87 ), 88 exuParameters = ExuParameters( 89 JmpCnt = 1, 90 AluCnt = 2, 91 MulCnt = 0, 92 MduCnt = 1, 93 FmacCnt = 1, 94 FmiscCnt = 1, 95 FmiscDivSqrtCnt = 0, 96 LduCnt = 2, 97 StuCnt = 2 98 ), 99 icacheParameters = ICacheParameters( 100 nSets = 64, // 16KB ICache 101 tagECC = Some("parity"), 102 dataECC = Some("parity"), 103 replacer = Some("setplru"), 104 nMissEntries = 2, 105 nReleaseEntries = 1, 106 nProbeEntries = 2, 107 nPrefetchEntries = 2, 108 nPrefBufferEntries = 32, 109 hasPrefetch = true 110 ), 111 dcacheParametersOpt = Some(DCacheParameters( 112 nSets = 64, // 32KB DCache 113 nWays = 8, 114 tagECC = Some("secded"), 115 dataECC = Some("secded"), 116 replacer = Some("setplru"), 117 nMissEntries = 4, 118 nProbeEntries = 4, 119 nReleaseEntries = 8, 120 )), 121 EnableBPD = false, // disable TAGE 122 EnableLoop = false, 123 itlbParameters = TLBParameters( 124 name = "itlb", 125 fetchi = true, 126 useDmode = false, 127 normalReplacer = Some("plru"), 128 superReplacer = Some("plru"), 129 normalNWays = 4, 130 normalNSets = 1, 131 superNWays = 2 132 ), 133 ldtlbParameters = TLBParameters( 134 name = "ldtlb", 135 normalNSets = 16, // when da or sa 136 normalNWays = 1, // when fa or sa 137 normalAssociative = "sa", 138 normalReplacer = Some("setplru"), 139 superNWays = 4, 140 normalAsVictim = true, 141 partialStaticPMP = true, 142 outsideRecvFlush = true, 143 outReplace = false 144 ), 145 sttlbParameters = TLBParameters( 146 name = "sttlb", 147 normalNSets = 16, // when da or sa 148 normalNWays = 1, // when fa or sa 149 normalAssociative = "sa", 150 normalReplacer = Some("setplru"), 151 normalAsVictim = true, 152 superNWays = 4, 153 partialStaticPMP = true, 154 outsideRecvFlush = true, 155 outReplace = false 156 ), 157 pftlbParameters = TLBParameters( 158 name = "pftlb", 159 normalNSets = 16, // when da or sa 160 normalNWays = 1, // when fa or sa 161 normalAssociative = "sa", 162 normalReplacer = Some("setplru"), 163 normalAsVictim = true, 164 superNWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false 168 ), 169 btlbParameters = TLBParameters( 170 name = "btlb", 171 normalNSets = 1, 172 normalNWays = 8, 173 superNWays = 2 174 ), 175 l2tlbParameters = L2TLBParameters( 176 l1Size = 4, 177 l2nSets = 4, 178 l2nWays = 4, 179 l3nSets = 4, 180 l3nWays = 8, 181 spSize = 2, 182 ), 183 L2CacheParamsOpt = None, // remove L2 Cache 184 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 185 ) 186 ) 187 case SoCParamsKey => 188 val tiles = site(XSTileKey) 189 up(SoCParamsKey).copy( 190 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 191 sets = 1024, 192 inclusive = false, 193 clientCaches = tiles.map{ p => 194 CacheParameters( 195 "dcache", 196 sets = 2 * p.dcacheParametersOpt.get.nSets, 197 ways = p.dcacheParametersOpt.get.nWays + 2, 198 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 199 aliasBitsOpt = None 200 ) 201 }, 202 simulation = !site(DebugOptionsKey).FPGAPlatform 203 )), 204 L3NBanks = 1 205 ) 206 }) 207) 208 209// Non-synthesizable MinimalConfig, for fast simulation only 210class MinimalSimConfig(n: Int = 1) extends Config( 211 new MinimalConfig(n).alter((site, here, up) => { 212 case XSTileKey => up(XSTileKey).map(_.copy( 213 dcacheParametersOpt = None, 214 softPTW = true 215 )) 216 case SoCParamsKey => up(SoCParamsKey).copy( 217 L3CacheParamsOpt = None 218 ) 219 }) 220) 221 222class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 223 case XSTileKey => 224 val sets = n * 1024 / ways / 64 225 up(XSTileKey).map(_.copy( 226 dcacheParametersOpt = Some(DCacheParameters( 227 nSets = sets, 228 nWays = ways, 229 tagECC = Some("secded"), 230 dataECC = Some("secded"), 231 replacer = Some("setplru"), 232 nMissEntries = 16, 233 nProbeEntries = 8, 234 nReleaseEntries = 18 235 )) 236 )) 237}) 238 239class WithNKBL2 240( 241 n: Int, 242 ways: Int = 8, 243 inclusive: Boolean = true, 244 banks: Int = 1, 245 alwaysReleaseData: Boolean = false 246) extends Config((site, here, up) => { 247 case XSTileKey => 248 val upParams = up(XSTileKey) 249 val l2sets = n * 1024 / banks / ways / 64 250 upParams.map(p => p.copy( 251 L2CacheParamsOpt = Some(HCCacheParameters( 252 name = "L2", 253 level = 2, 254 ways = ways, 255 sets = l2sets, 256 inclusive = inclusive, 257 alwaysReleaseData = alwaysReleaseData, 258 clientCaches = Seq(CacheParameters( 259 "dcache", 260 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 261 ways = p.dcacheParametersOpt.get.nWays + 2, 262 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 263 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 264 )), 265 reqField = Seq(PreferCacheField()), 266 echoField = Seq(DirtyField()), 267 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()), 268 enablePerf = true, 269 sramDepthDiv = 2, 270 tagECC = Some("secded"), 271 dataECC = Some("secded"), 272 simulation = !site(DebugOptionsKey).FPGAPlatform 273 )), 274 L2NBanks = banks 275 )) 276}) 277 278class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 279 case SoCParamsKey => 280 val sets = n * 1024 / banks / ways / 64 281 val tiles = site(XSTileKey) 282 val clientDirBytes = tiles.map{ t => 283 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 284 }.sum 285 up(SoCParamsKey).copy( 286 L3NBanks = banks, 287 L3CacheParamsOpt = Some(HCCacheParameters( 288 name = "L3", 289 level = 3, 290 ways = ways, 291 sets = sets, 292 inclusive = inclusive, 293 clientCaches = tiles.map{ core => 294 val l2params = core.L2CacheParamsOpt.get.toCacheParams 295 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 296 }, 297 enablePerf = true, 298 ctrl = Some(CacheCtrl( 299 address = 0x39000000, 300 numCores = tiles.size 301 )), 302 sramClkDivBy2 = true, 303 sramDepthDiv = 4, 304 tagECC = Some("secded"), 305 dataECC = Some("secded"), 306 simulation = !site(DebugOptionsKey).FPGAPlatform 307 )) 308 ) 309}) 310 311class WithL3DebugConfig extends Config( 312 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 313) 314 315class MinimalL3DebugConfig(n: Int = 1) extends Config( 316 new WithL3DebugConfig ++ new MinimalConfig(n) 317) 318 319class DefaultL3DebugConfig(n: Int = 1) extends Config( 320 new WithL3DebugConfig ++ new BaseConfig(n) 321) 322 323class MinimalAliasDebugConfig(n: Int = 1) extends Config( 324 new WithNKBL3(512, inclusive = false) ++ 325 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 326 new WithNKBL1D(128) ++ 327 new MinimalConfig(n) 328) 329 330class MediumConfig(n: Int = 1) extends Config( 331 new WithNKBL3(4096, inclusive = false, banks = 4) 332 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 333 ++ new WithNKBL1D(128) 334 ++ new BaseConfig(n) 335) 336 337class DefaultConfig(n: Int = 1) extends Config( 338 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 339 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 340 ++ new WithNKBL1D(128) 341 ++ new BaseConfig(n) 342) 343