1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import xiangshan.ExceptionNO._ 20import xiangshan.backend.exu._ 21import xiangshan.backend.fu._ 22import xiangshan.backend.fu.fpu._ 23import xiangshan.backend.fu.vector._ 24import xiangshan.backend.issue._ 25import xiangshan.v2backend.FuConfig 26 27package object xiangshan { 28 object SrcType { 29 def imm = "b000".U 30 def pc = "b000".U 31 def xp = "b001".U 32 def fp = "b010".U 33 def vp = "b100".U 34 35 // alias 36 def reg = this.xp 37 def DC = imm // Don't Care 38 def X = BitPat("b000") 39 40 def isPc(srcType: UInt) = srcType===pc 41 def isImm(srcType: UInt) = srcType===imm 42 def isReg(srcType: UInt) = srcType(0) 43 def isXp(srcType: UInt) = srcType(0) 44 def isFp(srcType: UInt) = srcType(1) 45 def isVp(srcType: UInt) = srcType(2) 46 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 47 def isNotReg(srcType: UInt): Bool = !srcType.orR 48 def apply() = UInt(3.W) 49 } 50 51 object SrcState { 52 def busy = "b0".U 53 def rdy = "b1".U 54 // def specRdy = "b10".U // speculative ready, for future use 55 def apply() = UInt(1.W) 56 57 def isReady(state: UInt): Bool = state === this.rdy 58 def isBusy(state: UInt): Bool = state === this.busy 59 } 60 61 // Todo: Use OH instead 62// object FuType { 63// def jmp = (BigInt(1) << 0).U 64// def brh = (BigInt(1) << 1).U 65// def i2f = (BigInt(1) << 2).U 66// def csr = (BigInt(1) << 3).U 67// def alu = (BigInt(1) << 4).U 68// def mul = (BigInt(1) << 5).U 69// def div = (BigInt(1) << 6).U 70// def fence = (BigInt(1) << 7).U 71// def bku = (BigInt(1) << 8).U 72// def vset = (BigInt(1) << 9).U 73// 74// def fmac = (BigInt(1) << 10).U 75// def fmisc = (BigInt(1) << 11).U 76// def fDivSqrt = (BigInt(1) << 12).U 77// 78// def ldu = (BigInt(1) << 13).U 79// def stu = (BigInt(1) << 14).U 80// def mou = (BigInt(1) << 15).U // for amo, lr, sc, fence 81// def vipu = (BigInt(1) << 16).U 82// def vfpu = (BigInt(1) << 17).U 83// def vldu = (BigInt(1) << 18).U 84// def vstu = (BigInt(1) << 19).U 85// def X = BitPat.dontCare(num) 86// 87// def num = 20 88// 89// def apply() = UInt(log2Up(num).W) 90// 91// def isIntExu(fuType: UInt) = !fuType(3) 92// def isJumpExu(fuType: UInt) = fuType === jmp 93// def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 94// def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 95// def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 96// def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 97// def isAMO(fuType: UInt) = fuType(1) 98// def isFence(fuType: UInt) = fuType === fence 99// def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 100// def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 101// def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 102// def isVpu(fuType: UInt) = fuType(4) 103// 104// def jmpCanAccept(fuType: UInt) = !fuType(2) 105// def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 106// def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 107// 108// def fmacCanAccept(fuType: UInt) = !fuType(1) 109// def fmiscCanAccept(fuType: UInt) = fuType(1) 110// 111// def loadCanAccept(fuType: UInt) = !fuType(0) 112// def storeCanAccept(fuType: UInt) = fuType(0) 113// 114// def storeIsAMO(fuType: UInt) = fuType(1) 115// 116// val functionNameMap = Map( 117// jmp.litValue() -> "jmp", 118// i2f.litValue() -> "int_to_float", 119// csr.litValue() -> "csr", 120// alu.litValue() -> "alu", 121// mul.litValue() -> "mul", 122// div.litValue() -> "div", 123// fence.litValue() -> "fence", 124// bku.litValue() -> "bku", 125// fmac.litValue() -> "fmac", 126// fmisc.litValue() -> "fmisc", 127// fDivSqrt.litValue() -> "fdiv_fsqrt", 128// ldu.litValue() -> "load", 129// stu.litValue() -> "store", 130// mou.litValue() -> "mou" 131// ) 132// } 133 134 def FuOpTypeWidth = 8 135 object FuOpType { 136 def apply() = UInt(FuOpTypeWidth.W) 137 def X = BitPat("b00000000") 138 } 139 140 // move VipuType and VfpuType into YunSuan/package.scala 141 // object VipuType { 142 // def dummy = 0.U(7.W) 143 // } 144 145 // object VfpuType { 146 // def dummy = 0.U(7.W) 147 // } 148 149 object VlduType { 150 def dummy = 0.U 151 } 152 153 object VstuType { 154 def dummy = 0.U 155 } 156 157 object CommitType { 158 def NORMAL = "b000".U // int/fp 159 def BRANCH = "b001".U // branch 160 def LOAD = "b010".U // load 161 def STORE = "b011".U // store 162 163 def apply() = UInt(3.W) 164 def isFused(commitType: UInt): Bool = commitType(2) 165 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 166 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 167 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 168 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 169 } 170 171 object RedirectLevel { 172 def flushAfter = "b0".U 173 def flush = "b1".U 174 175 def apply() = UInt(1.W) 176 // def isUnconditional(level: UInt) = level(1) 177 def flushItself(level: UInt) = level(0) 178 // def isException(level: UInt) = level(1) && level(0) 179 } 180 181 object ExceptionVec { 182 def apply() = Vec(16, Bool()) 183 } 184 185 object PMAMode { 186 def R = "b1".U << 0 //readable 187 def W = "b1".U << 1 //writeable 188 def X = "b1".U << 2 //executable 189 def I = "b1".U << 3 //cacheable: icache 190 def D = "b1".U << 4 //cacheable: dcache 191 def S = "b1".U << 5 //enable speculative access 192 def A = "b1".U << 6 //enable atomic operation, A imply R & W 193 def C = "b1".U << 7 //if it is cacheable is configable 194 def Reserved = "b0".U 195 196 def apply() = UInt(7.W) 197 198 def read(mode: UInt) = mode(0) 199 def write(mode: UInt) = mode(1) 200 def execute(mode: UInt) = mode(2) 201 def icache(mode: UInt) = mode(3) 202 def dcache(mode: UInt) = mode(4) 203 def speculate(mode: UInt) = mode(5) 204 def atomic(mode: UInt) = mode(6) 205 def configable_cache(mode: UInt) = mode(7) 206 207 def strToMode(s: String) = { 208 var result = 0.U(8.W) 209 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 210 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 211 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 212 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 213 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 214 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 215 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 216 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 217 result 218 } 219 } 220 221 222 object CSROpType { 223 def jmp = "b000".U 224 def wrt = "b001".U 225 def set = "b010".U 226 def clr = "b011".U 227 def wfi = "b100".U 228 def wrti = "b101".U 229 def seti = "b110".U 230 def clri = "b111".U 231 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 232 } 233 234 // jump 235 object JumpOpType { 236 def jal = "b00".U 237 def jalr = "b01".U 238 def auipc = "b10".U 239// def call = "b11_011".U 240// def ret = "b11_100".U 241 def jumpOpisJalr(op: UInt) = op(0) 242 def jumpOpisAuipc(op: UInt) = op(1) 243 } 244 245 object FenceOpType { 246 def fence = "b10000".U 247 def sfence = "b10001".U 248 def fencei = "b10010".U 249 def nofence= "b00000".U 250 } 251 252 object ALUOpType { 253 // shift optype 254 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 255 def sll = "b000_0001".U // sll: src1 << src2 256 257 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 258 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 259 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 260 261 def srl = "b000_0101".U // srl: src1 >> src2 262 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 263 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 264 265 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 266 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 267 268 // RV64 32bit optype 269 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 270 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 271 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 272 273 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 274 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 275 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 276 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 277 278 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 279 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 280 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 281 def rolw = "b001_1100".U 282 def rorw = "b001_1101".U 283 284 // ADD-op 285 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 286 def add = "b010_0001".U // add: src1 + src2 287 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 288 289 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 290 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 291 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 292 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 293 294 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 295 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 296 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 297 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 298 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 299 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 300 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 301 302 // SUB-op: src1 - src2 303 def sub = "b011_0000".U 304 def sltu = "b011_0001".U 305 def slt = "b011_0010".U 306 def maxu = "b011_0100".U 307 def minu = "b011_0101".U 308 def max = "b011_0110".U 309 def min = "b011_0111".U 310 311 // branch 312 def beq = "b111_0000".U 313 def bne = "b111_0010".U 314 def blt = "b111_1000".U 315 def bge = "b111_1010".U 316 def bltu = "b111_1100".U 317 def bgeu = "b111_1110".U 318 319 // misc optype 320 def and = "b100_0000".U 321 def andn = "b100_0001".U 322 def or = "b100_0010".U 323 def orn = "b100_0011".U 324 def xor = "b100_0100".U 325 def xnor = "b100_0101".U 326 def orcb = "b100_0110".U 327 328 def sextb = "b100_1000".U 329 def packh = "b100_1001".U 330 def sexth = "b100_1010".U 331 def packw = "b100_1011".U 332 333 def revb = "b101_0000".U 334 def rev8 = "b101_0001".U 335 def pack = "b101_0010".U 336 def orh48 = "b101_0011".U 337 338 def szewl1 = "b101_1000".U 339 def szewl2 = "b101_1001".U 340 def szewl3 = "b101_1010".U 341 def byte2 = "b101_1011".U 342 343 def andlsb = "b110_0000".U 344 def andzexth = "b110_0001".U 345 def orlsb = "b110_0010".U 346 def orzexth = "b110_0011".U 347 def xorlsb = "b110_0100".U 348 def xorzexth = "b110_0101".U 349 def orcblsb = "b110_0110".U 350 def orcbzexth = "b110_0111".U 351 def vsetvli1 = "b1000_0000".U 352 def vsetvli2 = "b1000_0100".U 353 def vsetvl1 = "b1000_0001".U 354 def vsetvl2 = "b1000_0101".U 355 def vsetivli1 = "b1000_0010".U 356 def vsetivli2 = "b1000_0110".U 357 358 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 359 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 360 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 361 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 362 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 363 def isVsetvl(func: UInt) = isVset(func) && func(0) 364 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 365 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 366 367 def apply() = UInt(FuOpTypeWidth.W) 368 } 369 370 object BRUOpType { 371 // branch 372 def beq = "b000_000".U 373 def bne = "b000_001".U 374 def blt = "b000_100".U 375 def bge = "b000_101".U 376 def bltu = "b001_000".U 377 def bgeu = "b001_001".U 378 379 def getBranchType(func: UInt) = func(3, 1) 380 def isBranchInvert(func: UInt) = func(0) 381 } 382 383 object MULOpType { 384 // mul 385 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 386 def mul = "b00000".U 387 def mulh = "b00001".U 388 def mulhsu = "b00010".U 389 def mulhu = "b00011".U 390 def mulw = "b00100".U 391 392 def mulw7 = "b01100".U 393 def isSign(op: UInt) = !op(1) 394 def isW(op: UInt) = op(2) 395 def isH(op: UInt) = op(1, 0) =/= 0.U 396 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 397 } 398 399 object DIVOpType { 400 // div 401 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 402 def div = "b10000".U 403 def divu = "b10010".U 404 def rem = "b10001".U 405 def remu = "b10011".U 406 407 def divw = "b10100".U 408 def divuw = "b10110".U 409 def remw = "b10101".U 410 def remuw = "b10111".U 411 412 def isSign(op: UInt) = !op(1) 413 def isW(op: UInt) = op(2) 414 def isH(op: UInt) = op(0) 415 } 416 417 object MDUOpType { 418 // mul 419 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 420 def mul = "b00000".U 421 def mulh = "b00001".U 422 def mulhsu = "b00010".U 423 def mulhu = "b00011".U 424 def mulw = "b00100".U 425 426 def mulw7 = "b01100".U 427 428 // div 429 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 430 def div = "b10000".U 431 def divu = "b10010".U 432 def rem = "b10001".U 433 def remu = "b10011".U 434 435 def divw = "b10100".U 436 def divuw = "b10110".U 437 def remw = "b10101".U 438 def remuw = "b10111".U 439 440 def isMul(op: UInt) = !op(4) 441 def isDiv(op: UInt) = op(4) 442 443 def isDivSign(op: UInt) = isDiv(op) && !op(1) 444 def isW(op: UInt) = op(2) 445 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 446 def getMulOp(op: UInt) = op(1, 0) 447 } 448 449 object LSUOpType { 450 // load pipeline 451 452 // normal load 453 // Note: bit(1, 0) are size, DO NOT CHANGE 454 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 455 def lb = "b0000".U 456 def lh = "b0001".U 457 def lw = "b0010".U 458 def ld = "b0011".U 459 def lbu = "b0100".U 460 def lhu = "b0101".U 461 def lwu = "b0110".U 462 463 // Zicbop software prefetch 464 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 465 def prefetch_i = "b1000".U // TODO 466 def prefetch_r = "b1001".U 467 def prefetch_w = "b1010".U 468 469 def isPrefetch(op: UInt): Bool = op(3) 470 471 // store pipeline 472 // normal store 473 // bit encoding: | store 00 | size(2bit) | 474 def sb = "b0000".U 475 def sh = "b0001".U 476 def sw = "b0010".U 477 def sd = "b0011".U 478 479 // l1 cache op 480 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 481 def cbo_zero = "b0111".U 482 483 // llc op 484 // bit encoding: | prefetch 11 | suboptype(2bit) | 485 def cbo_clean = "b1100".U 486 def cbo_flush = "b1101".U 487 def cbo_inval = "b1110".U 488 489 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 490 491 // atomics 492 // bit(1, 0) are size 493 // since atomics use a different fu type 494 // so we can safely reuse other load/store's encodings 495 // bit encoding: | optype(4bit) | size (2bit) | 496 def lr_w = "b000010".U 497 def sc_w = "b000110".U 498 def amoswap_w = "b001010".U 499 def amoadd_w = "b001110".U 500 def amoxor_w = "b010010".U 501 def amoand_w = "b010110".U 502 def amoor_w = "b011010".U 503 def amomin_w = "b011110".U 504 def amomax_w = "b100010".U 505 def amominu_w = "b100110".U 506 def amomaxu_w = "b101010".U 507 508 def lr_d = "b000011".U 509 def sc_d = "b000111".U 510 def amoswap_d = "b001011".U 511 def amoadd_d = "b001111".U 512 def amoxor_d = "b010011".U 513 def amoand_d = "b010111".U 514 def amoor_d = "b011011".U 515 def amomin_d = "b011111".U 516 def amomax_d = "b100011".U 517 def amominu_d = "b100111".U 518 def amomaxu_d = "b101011".U 519 520 def size(op: UInt) = op(1,0) 521 } 522 523 object BKUOpType { 524 525 def clmul = "b000000".U 526 def clmulh = "b000001".U 527 def clmulr = "b000010".U 528 def xpermn = "b000100".U 529 def xpermb = "b000101".U 530 531 def clz = "b001000".U 532 def clzw = "b001001".U 533 def ctz = "b001010".U 534 def ctzw = "b001011".U 535 def cpop = "b001100".U 536 def cpopw = "b001101".U 537 538 // 01xxxx is reserve 539 def aes64es = "b100000".U 540 def aes64esm = "b100001".U 541 def aes64ds = "b100010".U 542 def aes64dsm = "b100011".U 543 def aes64im = "b100100".U 544 def aes64ks1i = "b100101".U 545 def aes64ks2 = "b100110".U 546 547 // merge to two instruction sm4ks & sm4ed 548 def sm4ed0 = "b101000".U 549 def sm4ed1 = "b101001".U 550 def sm4ed2 = "b101010".U 551 def sm4ed3 = "b101011".U 552 def sm4ks0 = "b101100".U 553 def sm4ks1 = "b101101".U 554 def sm4ks2 = "b101110".U 555 def sm4ks3 = "b101111".U 556 557 def sha256sum0 = "b110000".U 558 def sha256sum1 = "b110001".U 559 def sha256sig0 = "b110010".U 560 def sha256sig1 = "b110011".U 561 def sha512sum0 = "b110100".U 562 def sha512sum1 = "b110101".U 563 def sha512sig0 = "b110110".U 564 def sha512sig1 = "b110111".U 565 566 def sm3p0 = "b111000".U 567 def sm3p1 = "b111001".U 568 } 569 570 object BTBtype { 571 def B = "b00".U // branch 572 def J = "b01".U // jump 573 def I = "b10".U // indirect 574 def R = "b11".U // return 575 576 def apply() = UInt(2.W) 577 } 578 579 object SelImm { 580 def IMM_X = "b0111".U 581 def IMM_S = "b0000".U 582 def IMM_SB = "b0001".U 583 def IMM_U = "b0010".U 584 def IMM_UJ = "b0011".U 585 def IMM_I = "b0100".U 586 def IMM_Z = "b0101".U 587 def INVALID_INSTR = "b0110".U 588 def IMM_B6 = "b1000".U 589 590 def IMM_OPIVIS = "b1001".U 591 def IMM_OPIVIU = "b1010".U 592 def IMM_VSETVLI = "b1100".U 593 def IMM_VSETIVLI = "b1101".U 594 595 def X = BitPat("b0000") 596 597 def apply() = UInt(4.W) 598 } 599 600 object ExceptionNO { 601 def instrAddrMisaligned = 0 602 def instrAccessFault = 1 603 def illegalInstr = 2 604 def breakPoint = 3 605 def loadAddrMisaligned = 4 606 def loadAccessFault = 5 607 def storeAddrMisaligned = 6 608 def storeAccessFault = 7 609 def ecallU = 8 610 def ecallS = 9 611 def ecallM = 11 612 def instrPageFault = 12 613 def loadPageFault = 13 614 // def singleStep = 14 615 def storePageFault = 15 616 def priorities = Seq( 617 breakPoint, // TODO: different BP has different priority 618 instrPageFault, 619 instrAccessFault, 620 illegalInstr, 621 instrAddrMisaligned, 622 ecallM, ecallS, ecallU, 623 storeAddrMisaligned, 624 loadAddrMisaligned, 625 storePageFault, 626 loadPageFault, 627 storeAccessFault, 628 loadAccessFault 629 ) 630 def all = priorities.distinct.sorted 631 def frontendSet = Seq( 632 instrAddrMisaligned, 633 instrAccessFault, 634 illegalInstr, 635 instrPageFault 636 ) 637 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 638 val new_vec = Wire(ExceptionVec()) 639 new_vec.foreach(_ := false.B) 640 select.foreach(i => new_vec(i) := vec(i)) 641 new_vec 642 } 643 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 644 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 645 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 646 partialSelect(vec, fuConfig.exceptionOut) 647// def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 648// partialSelect(vec, exuConfig.exceptionOut) 649// def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 650// partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 651 } 652 653// def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 654// def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 655// def aluGen(p: Parameters) = new Alu()(p) 656// def bkuGen(p: Parameters) = new Bku()(p) 657// def jmpGen(p: Parameters) = new Jump()(p) 658// def fenceGen(p: Parameters) = new Fence()(p) 659// def csrGen(p: Parameters) = new CSR()(p) 660// def i2fGen(p: Parameters) = new IntToFP()(p) 661// def fmacGen(p: Parameters) = new FMA()(p) 662// def f2iGen(p: Parameters) = new FPToInt()(p) 663// def f2fGen(p: Parameters) = new FPToFP()(p) 664// def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 665// def stdGen(p: Parameters) = new Std()(p) 666// def mouDataGen(p: Parameters) = new Std()(p) 667// def vipuGen(p: Parameters) = new VIPU()(p) 668// 669// def f2iSel(uop: MicroOp): Bool = { 670// uop.ctrl.rfWen 671// } 672// 673// def i2fSel(uop: MicroOp): Bool = { 674// uop.ctrl.fpu.fromInt 675// } 676// 677// def f2fSel(uop: MicroOp): Bool = { 678// val ctrl = uop.ctrl.fpu 679// ctrl.fpWen && !ctrl.div && !ctrl.sqrt 680// } 681// 682// def fdivSqrtSel(uop: MicroOp): Bool = { 683// val ctrl = uop.ctrl.fpu 684// ctrl.div || ctrl.sqrt 685// } 686// 687// val aluCfg = FuConfig( 688// name = "alu", 689// fuGen = aluGen, 690// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 691// fuType = FuType.alu, 692// numIntSrc = 2, 693// numFpSrc = 0, 694// writeIntRf = true, 695// writeFpRf = false, 696// hasRedirect = true, 697// ) 698// 699// val jmpCfg = FuConfig( 700// name = "jmp", 701// fuGen = jmpGen, 702// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 703// fuType = FuType.jmp, 704// numIntSrc = 1, 705// numFpSrc = 0, 706// writeIntRf = true, 707// writeFpRf = false, 708// hasRedirect = true, 709// ) 710// 711// val fenceCfg = FuConfig( 712// name = "fence", 713// fuGen = fenceGen, 714// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 715// FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 716// latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 717// flushPipe = true 718// ) 719// 720// val csrCfg = FuConfig( 721// name = "csr", 722// fuGen = csrGen, 723// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 724// fuType = FuType.csr, 725// numIntSrc = 1, 726// numFpSrc = 0, 727// writeIntRf = true, 728// writeFpRf = false, 729// exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 730// flushPipe = true 731// ) 732// 733// val i2fCfg = FuConfig( 734// name = "i2f", 735// fuGen = i2fGen, 736// fuSel = i2fSel, 737// FuType.i2f, 738// numIntSrc = 1, 739// numFpSrc = 0, 740// writeIntRf = false, 741// writeFpRf = true, 742// writeFflags = true, 743// latency = CertainLatency(2), 744// fastUopOut = true, fastImplemented = true 745// ) 746// 747// val divCfg = FuConfig( 748// name = "div", 749// fuGen = dividerGen, 750// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 751// FuType.div, 752// 2, 753// 0, 754// writeIntRf = true, 755// writeFpRf = false, 756// latency = UncertainLatency(), 757// fastUopOut = true, 758// fastImplemented = true, 759// hasInputBuffer = (true, 4, true) 760// ) 761// 762// val mulCfg = FuConfig( 763// name = "mul", 764// fuGen = multiplierGen, 765// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 766// FuType.mul, 767// 2, 768// 0, 769// writeIntRf = true, 770// writeFpRf = false, 771// latency = CertainLatency(2), 772// fastUopOut = true, 773// fastImplemented = true 774// ) 775// 776// val bkuCfg = FuConfig( 777// name = "bku", 778// fuGen = bkuGen, 779// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 780// fuType = FuType.bku, 781// numIntSrc = 2, 782// numFpSrc = 0, 783// writeIntRf = true, 784// writeFpRf = false, 785// latency = CertainLatency(1), 786// fastUopOut = true, 787// fastImplemented = true 788// ) 789// 790// val fmacCfg = FuConfig( 791// name = "fmac", 792// fuGen = fmacGen, 793// fuSel = _ => true.B, 794// FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 795// latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 796// ) 797// 798// val f2iCfg = FuConfig( 799// name = "f2i", 800// fuGen = f2iGen, 801// fuSel = f2iSel, 802// FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 803// fastUopOut = true, fastImplemented = true 804// ) 805// 806// val f2fCfg = FuConfig( 807// name = "f2f", 808// fuGen = f2fGen, 809// fuSel = f2fSel, 810// FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 811// fastUopOut = true, fastImplemented = true 812// ) 813// 814// val fdivSqrtCfg = FuConfig( 815// name = "fdivSqrt", 816// fuGen = fdivSqrtGen, 817// fuSel = fdivSqrtSel, 818// FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 819// fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 820// ) 821// 822// val lduCfg = FuConfig( 823// "ldu", 824// null, // DontCare 825// (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 826// FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 827// latency = UncertainLatency(), 828// exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 829// flushPipe = true, 830// replayInst = true, 831// hasLoadError = true 832// ) 833// 834// val staCfg = FuConfig( 835// "sta", 836// null, 837// (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 838// FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 839// latency = UncertainLatency(), 840// exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 841// ) 842// 843// val stdCfg = FuConfig( 844// "std", 845// fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 846// writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 847// ) 848// 849// val mouCfg = FuConfig( 850// "mou", 851// null, 852// (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 853// FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 854// latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 855// ) 856// 857// val mouDataCfg = FuConfig( 858// "mou", 859// mouDataGen, 860// (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 861// FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 862// latency = UncertainLatency() 863// ) 864// 865// val vipuCfg = FuConfig( 866// name = "vipu", 867// fuGen = vipuGen, 868// fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 869// fuType = FuType.vipu, 870// numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 871// numVecSrc = 2, writeVecRf = true, 872// fastUopOut = true, // TODO: check 873// fastImplemented = true, //TODO: check 874// ) 875 876// val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 877// val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 878// val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 879// val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 880// val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 881// val FmiscExeUnitCfg = ExuConfig( 882// "FmiscExeUnit", 883// "Fp", 884// Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 885// Int.MaxValue, 1 886// ) 887// val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 888// val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 889// val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 890 891 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 892 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 893 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 894 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 895 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 896 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 897 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 898 899// val aluRSMod = new RSMod( 900// rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 901// rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 902// immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 903// ) 904// val fmaRSMod = new RSMod( 905// rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 906// rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 907// ) 908// val fmiscRSMod = new RSMod( 909// rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 910// rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 911// ) 912// val jumpRSMod = new RSMod( 913// rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 914// rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 915// immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 916// ) 917// val loadRSMod = new RSMod( 918// rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 919// rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 920// immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 921// ) 922// val mulRSMod = new RSMod( 923// rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 924// rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 925// immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 926// ) 927// val staRSMod = new RSMod( 928// rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 929// rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 930// ) 931// val stdRSMod = new RSMod( 932// rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 933// rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 934// ) 935} 936