1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import freechips.rocketchip.tilelink.TLBuffer 27import system.HasSoCParameter 28import utility._ 29import utils._ 30import xiangshan.backend._ 31import xiangshan.cache.mmu._ 32import xiangshan.frontend._ 33import xiangshan.v2backend._ 34 35abstract class XSModule(implicit val p: Parameters) extends Module 36 with HasXSParameter 37 with HasFPUParameters 38 39//remove this trait after impl module logic 40trait NeedImpl { 41 this: RawModule => 42 override protected def IO[T <: Data](iodef: T): T = { 43 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 44 val io = chisel3.experimental.IO(iodef) 45 io <> DontCare 46 io 47 } 48} 49 50//class WritebackSourceParams( 51// var exuConfigs: Seq[Seq[ExuConfig]] = Seq() 52// ) { 53// def length: Int = exuConfigs.length 54// def ++(that: WritebackSourceParams): WritebackSourceParams = { 55// new WritebackSourceParams(exuConfigs ++ that.exuConfigs) 56// } 57//} 58 59//trait HasWritebackSource { 60// val writebackSourceParams: Seq[WritebackSourceParams] 61// final def writebackSource(sourceMod: HasWritebackSourceImp): Seq[Seq[Valid[ExuOutput]]] = { 62// require(sourceMod.writebackSource.isDefined, "should not use Valid[ExuOutput]") 63// val source = sourceMod.writebackSource.get 64// require(source.length == writebackSourceParams.length, "length mismatch between sources") 65// for ((s, p) <- source.zip(writebackSourceParams)) { 66// require(s.length == p.length, "params do not match with the exuOutput") 67// } 68// source 69// } 70// final def writebackSource1(sourceMod: HasWritebackSourceImp): Seq[Seq[DecoupledIO[ExuOutput]]] = { 71// require(sourceMod.writebackSource1.isDefined, "should not use DecoupledIO[ExuOutput]") 72// val source = sourceMod.writebackSource1.get 73// require(source.length == writebackSourceParams.length, "length mismatch between sources") 74// for ((s, p) <- source.zip(writebackSourceParams)) { 75// require(s.length == p.length, "params do not match with the exuOutput") 76// } 77// source 78// } 79// val writebackSourceImp: HasWritebackSourceImp 80//} 81 82//trait HasWritebackSourceImp { 83// def writebackSource: Option[Seq[Seq[Valid[ExuOutput]]]] = None 84// def writebackSource1: Option[Seq[Seq[DecoupledIO[ExuOutput]]]] = None 85//} 86 87//trait HasWritebackSink { 88// // Caches all sources. The selected source will be the one with smallest length. 89// var writebackSinks = ListBuffer.empty[(Seq[HasWritebackSource], Seq[Int])] 90// def addWritebackSink(source: Seq[HasWritebackSource], index: Option[Seq[Int]] = None): HasWritebackSink = { 91// val realIndex = if (index.isDefined) index.get else Seq.fill(source.length)(0) 92// writebackSinks += ((source, realIndex)) 93// this 94// } 95// 96// def writebackSinksParams: Seq[WritebackSourceParams] = { 97// writebackSinks.map{ case (s, i) => s.zip(i).map(x => x._1.writebackSourceParams(x._2)).reduce(_ ++ _) } 98// } 99// final def writebackSinksMod( 100// thisMod: Option[HasWritebackSource] = None, 101// thisModImp: Option[HasWritebackSourceImp] = None 102// ): Seq[Seq[HasWritebackSourceImp]] = { 103// require(thisMod.isDefined == thisModImp.isDefined) 104// writebackSinks.map(_._1.map(source => 105// if (thisMod.isDefined && source == thisMod.get) thisModImp.get else source.writebackSourceImp) 106// ) 107// } 108// final def writebackSinksImp( 109// thisMod: Option[HasWritebackSource] = None, 110// thisModImp: Option[HasWritebackSourceImp] = None 111// ): Seq[Seq[ValidIO[ExuOutput]]] = { 112// val sourceMod = writebackSinksMod(thisMod, thisModImp) 113// writebackSinks.zip(sourceMod).map{ case ((s, i), m) => 114// s.zip(i).zip(m).flatMap(x => x._1._1.writebackSource(x._2)(x._1._2)) 115// } 116// } 117// def selWritebackSinks(func: WritebackSourceParams => Int): Int = { 118// writebackSinksParams.zipWithIndex.minBy(params => func(params._1))._2 119// } 120// def generateWritebackIO( 121// thisMod: Option[HasWritebackSource] = None, 122// thisModImp: Option[HasWritebackSourceImp] = None 123// ): Unit 124//} 125 126abstract class XSBundle(implicit val p: Parameters) extends Bundle 127 with HasXSParameter 128 129abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 130 with HasXSParameter 131{ 132 // interrupt sinks 133 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 134 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 135 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 136 // outer facing nodes 137 val frontend = LazyModule(new Frontend()) 138 val ptw = LazyModule(new L2TLBWrapper()) 139 val ptw_to_l2_buffer = if (!coreParams.softPTW) LazyModule(new TLBuffer) else null 140 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 141 val backend = LazyModule(new Backend(backendParams)) 142 143 if (!coreParams.softPTW) { 144 ptw_to_l2_buffer.node := ptw.node 145 } 146 147 val memBlock = LazyModule(new MemBlock()(p.alter((site, here, up) => { 148 case XSCoreParamsKey => up(XSCoreParamsKey).copy( 149 IssQueSize = 16 // Todo 150 ) 151 }))) 152} 153 154class XSCore()(implicit p: config.Parameters) extends XSCoreBase 155 with HasXSDts 156{ 157 lazy val module = new XSCoreImp(this) 158} 159 160class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 161 with HasXSParameter 162 with HasSoCParameter { 163 val io = IO(new Bundle { 164 val hartId = Input(UInt(64.W)) 165 val reset_vector = Input(UInt(PAddrBits.W)) 166 val cpu_halt = Output(Bool()) 167 val l2_pf_enable = Output(Bool()) 168 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 169 val beu_errors = Output(new XSL1BusErrors()) 170 }) 171 172 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 173 174 val frontend = outer.frontend.module 175 val backend = outer.backend.module 176 val memBlock = outer.memBlock.module 177 val ptw = outer.ptw.module 178 val ptw_to_l2_buffer = if (!coreParams.softPTW) outer.ptw_to_l2_buffer.module else null 179 180 val csrioIn = backend.io.csr 181 val fenceio = backend.io.fenceio 182 183 frontend.io.hartId := io.hartId 184 frontend.io.backend <> backend.io.frontend 185 frontend.io.sfence <> backend.io.frontendSfence 186 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 187 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 188 frontend.io.fencei <> fenceio.fencei 189 190 backend.io.fromTop.hartId := io.hartId 191 backend.io.mem.stIn := 0.U.asTypeOf(backend.io.mem.stIn) // Todo <> memBlock.io.stIn 192 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 193 backend.io.mem.enqLsq <> memBlock.io.enqLsq 194 backend.io.mem.sqDeq := memBlock.io.sqDeq 195 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 196 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 197 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 198 199 memBlock.io.issue <> 0.U.asTypeOf(memBlock.io.issue) 200 201 memBlock.io.hartId := io.hartId 202 frontend.io.reset_vector := io.reset_vector 203 204 io.cpu_halt := backend.io.toTop.cpuHalted 205 206 // memblock error exception writeback, 1 cycle after normal writeback 207 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 208 209 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 210 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 211 212 memBlock.io.issue <> backend.io.mem.issueUops 213 // By default, instructions do not have exceptions when they enter the function units. 214 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 215 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 216 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 217 218// XSPerfHistogram("fastIn_count", PopCount(allFastUop1.map(_.valid)), true.B, 0, allFastUop1.length, 1) 219// XSPerfHistogram("wakeup_count", PopCount(rfWriteback.map(_.valid)), true.B, 0, rfWriteback.length, 1) 220 221// ctrlBlock.perfinfo.perfEventsEu0 := intExuBlock.getPerf.dropRight(outer.intExuBlock.scheduler.numRs) 222// ctrlBlock.perfinfo.perfEventsEu1 := vecExuBlock.getPerf.dropRight(outer.vecExuBlock.scheduler.numRs) 223 if (!coreParams.softPTW) { 224 memBlock.io.perfEventsPTW := ptw.getPerf 225 } else { 226 memBlock.io.perfEventsPTW := DontCare 227 } 228// ctrlBlock.perfinfo.perfEventsRs := outer.exuBlocks.flatMap(b => b.module.getPerf.takeRight(b.scheduler.numRs)) 229 230 csrioIn.perf.memInfo <> memBlock.io.memInfo 231 csrioIn.perf.frontendInfo <> frontend.io.frontendInfo 232 233 csrioIn.perf.perfEventsFrontend <> frontend.getPerf 234 csrioIn.perf.perfEventsLsu <> memBlock.getPerf 235 csrioIn.perf.perfEventsHc <> io.perfEvents 236 csrioIn.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 237 238 csrioIn.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 239 csrioIn.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 240 csrioIn.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 241 csrioIn.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 242 csrioIn.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 243 244 csrioIn.distributedUpdate(0).w.valid := memBlock.io.csrUpdate.w.valid 245 csrioIn.distributedUpdate(0).w.bits := memBlock.io.csrUpdate.w.bits 246 csrioIn.distributedUpdate(1).w.valid := frontend.io.csrUpdate.w.valid 247 csrioIn.distributedUpdate(1).w.bits := frontend.io.csrUpdate.w.bits 248 249 memBlock.io.sfence <> backend.io.mem.sfence 250 memBlock.io.fenceToSbuffer <> backend.io.mem.toSbuffer 251 252 memBlock.io.redirect <> backend.io.redirect 253 memBlock.io.rsfeedback <> backend.io.mem.rsFeedBack 254 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 255 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 256 memBlock.io.lsqio.rob <> backend.io.mem.lsq 257 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 258 259 val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay,frontend.io.ptw, fenceio.sfence, csrioIn.tlb, l2tlbParams.ifilterSize) 260 val itlbRepeater2 = PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, ptw.io.tlb(0), fenceio.sfence, csrioIn.tlb) 261 val dtlbRepeater1 = PTWFilter(ldtlbParams.fenceDelay, memBlock.io.ptw, fenceio.sfence, csrioIn.tlb, l2tlbParams.dfilterSize) 262 val dtlbRepeater2 = PTWRepeaterNB(passReady = false, ldtlbParams.fenceDelay, dtlbRepeater1.io.ptw, ptw.io.tlb(1), fenceio.sfence, csrioIn.tlb) 263 ptw.io.sfence <> fenceio.sfence 264 ptw.io.csr.tlb <> csrioIn.tlb 265 ptw.io.csr.distribute_csr <> csrioIn.customCtrl.distribute_csr 266 267 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 268 io.l2_pf_enable := csrioIn.customCtrl.l2_pf_enable 269 270 // Modules are reset one by one 271 val resetTree = ResetGenNode( 272 Seq( 273 ModuleNode(memBlock), ModuleNode(dtlbRepeater1), 274 ResetGenNode(Seq( 275 ModuleNode(itlbRepeater2), 276 ModuleNode(ptw), 277 ModuleNode(dtlbRepeater2), 278 ModuleNode(ptw_to_l2_buffer), 279 )), 280 ResetGenNode(Seq( 281 ModuleNode(backend), 282 ResetGenNode(Seq( 283 ResetGenNode(Seq( 284 ModuleNode(frontend), ModuleNode(itlbRepeater1) 285 )) 286 )) 287 )) 288 ) 289 ) 290 291 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 292 293} 294