1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend._ 35import xiangshan.frontend.icache.ICacheParameters 36 37import freechips.rocketchip.diplomacy.AddressSet 38import system.SoCParamsKey 39import huancun._ 40import huancun.debug._ 41import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 42 43import scala.math.min 44 45case object XSTileKey extends Field[Seq[XSCoreParameters]] 46 47case object XSCoreParamsKey extends Field[XSCoreParameters] 48 49case class XSCoreParameters 50( 51 HasPrefetch: Boolean = false, 52 HartId: Int = 0, 53 XLEN: Int = 64, 54 VLEN: Int = 128, 55 HasMExtension: Boolean = true, 56 HasCExtension: Boolean = true, 57 HasDiv: Boolean = true, 58 HasICache: Boolean = true, 59 HasDCache: Boolean = true, 60 AddrBits: Int = 64, 61 VAddrBits: Int = 39, 62 HasFPU: Boolean = true, 63 HasVPU: Boolean = true, 64 HasCustomCSRCacheOp: Boolean = true, 65 FetchWidth: Int = 8, 66 AsidLength: Int = 16, 67 EnableBPU: Boolean = true, 68 EnableBPD: Boolean = true, 69 EnableRAS: Boolean = true, 70 EnableLB: Boolean = false, 71 EnableLoop: Boolean = true, 72 EnableSC: Boolean = true, 73 EnbaleTlbDebug: Boolean = false, 74 EnableJal: Boolean = false, 75 EnableFauFTB: Boolean = true, 76 UbtbGHRLength: Int = 4, 77 // HistoryLength: Int = 512, 78 EnableGHistDiff: Boolean = true, 79 UbtbSize: Int = 256, 80 FtbSize: Int = 2048, 81 RasSize: Int = 32, 82 CacheLineSize: Int = 512, 83 FtbWays: Int = 4, 84 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 85 // Sets Hist Tag 86 // Seq(( 2048, 2, 8), 87 // ( 2048, 9, 8), 88 // ( 2048, 13, 8), 89 // ( 2048, 20, 8), 90 // ( 2048, 26, 8), 91 // ( 2048, 44, 8), 92 // ( 2048, 73, 8), 93 // ( 2048, 256, 8)), 94 Seq(( 4096, 8, 8), 95 ( 4096, 13, 8), 96 ( 4096, 32, 8), 97 ( 4096, 119, 8)), 98 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 99 // Sets Hist Tag 100 Seq(( 256, 4, 9), 101 ( 256, 8, 9), 102 ( 512, 13, 9), 103 ( 512, 16, 9), 104 ( 512, 32, 9)), 105 SCNRows: Int = 512, 106 SCNTables: Int = 4, 107 SCCtrBits: Int = 6, 108 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 109 numBr: Int = 2, 110 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 111 ((resp_in: BranchPredictionResp, p: Parameters) => { 112 val ftb = Module(new FTB()(p)) 113 val ubtb =Module(new FauFTB()(p)) 114 // val bim = Module(new BIM()(p)) 115 val tage = Module(new Tage_SC()(p)) 116 val ras = Module(new RAS()(p)) 117 val ittage = Module(new ITTage()(p)) 118 val preds = Seq(ubtb, tage, ftb, ittage, ras) 119 preds.map(_.io := DontCare) 120 121 // ubtb.io.resp_in(0) := resp_in 122 // bim.io.resp_in(0) := ubtb.io.resp 123 // btb.io.resp_in(0) := bim.io.resp 124 // tage.io.resp_in(0) := btb.io.resp 125 // loop.io.resp_in(0) := tage.io.resp 126 ubtb.io.in.bits.resp_in(0) := resp_in 127 tage.io.in.bits.resp_in(0) := ubtb.io.out 128 ftb.io.in.bits.resp_in(0) := tage.io.out 129 ittage.io.in.bits.resp_in(0) := ftb.io.out 130 ras.io.in.bits.resp_in(0) := ittage.io.out 131 132 (preds, ras.io.out) 133 }), 134 IBufSize: Int = 48, 135 DecodeWidth: Int = 6, 136 RenameWidth: Int = 6, 137 CommitWidth: Int = 6, 138 FtqSize: Int = 64, 139 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 140 NRPhyRegs: Int = 192, 141 IntPhyRegs: Int = 192, 142 VfPhyRegs: Int = 192, 143 LoadQueueSize: Int = 80, 144 LoadQueueNWriteBanks: Int = 8, 145 StoreQueueSize: Int = 64, 146 StoreQueueNWriteBanks: Int = 8, 147 VlsQueueSize: Int = 8, 148 RobSize: Int = 256, 149 dpParams: DispatchParameters = DispatchParameters( 150 IntDqSize = 16, 151 FpDqSize = 16, 152 LsDqSize = 16, 153 IntDqDeqWidth = 6, 154 FpDqDeqWidth = 6, 155 LsDqDeqWidth = 6, 156 ), 157 intPreg: PregParams = IntPregParams( 158 numEntries = 64, 159 numRead = 14, 160 numWrite = 8, 161 ), 162 vfPreg: VfPregParams = VfPregParams( 163 numEntries = 64, 164 numRead = 14, 165 numWrite = 8, 166 ), 167 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 168 LoadPipelineWidth: Int = 2, 169 StorePipelineWidth: Int = 2, 170 VecMemSrcInWidth: Int = 2, 171 VecMemInstWbWidth: Int = 1, 172 VecMemDispatchWidth: Int = 1, 173 StoreBufferSize: Int = 16, 174 StoreBufferThreshold: Int = 7, 175 EnsbufferWidth: Int = 2, 176 UncacheBufferSize: Int = 4, 177 EnableLoadToLoadForward: Boolean = true, 178 EnableFastForward: Boolean = false, 179 EnableLdVioCheckAfterReset: Boolean = true, 180 EnableSoftPrefetchAfterReset: Boolean = true, 181 EnableCacheErrorAfterReset: Boolean = true, 182 EnableDCacheWPU: Boolean = false, 183 EnableAccurateLoadError: Boolean = true, 184 EnableUncacheWriteOutstanding: Boolean = false, 185 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 186 ReSelectLen: Int = 7, // load replay queue replay select counter len 187 itlbParameters: TLBParameters = TLBParameters( 188 name = "itlb", 189 fetchi = true, 190 useDmode = false, 191 normalNWays = 32, 192 normalReplacer = Some("plru"), 193 superNWays = 4, 194 superReplacer = Some("plru") 195 ), 196 ldtlbParameters: TLBParameters = TLBParameters( 197 name = "ldtlb", 198 normalNSets = 64, 199 normalNWays = 1, 200 normalAssociative = "sa", 201 normalReplacer = Some("setplru"), 202 superNWays = 16, 203 normalAsVictim = true, 204 outReplace = false, 205 partialStaticPMP = true, 206 outsideRecvFlush = true, 207 saveLevel = true 208 ), 209 sttlbParameters: TLBParameters = TLBParameters( 210 name = "sttlb", 211 normalNSets = 64, 212 normalNWays = 1, 213 normalAssociative = "sa", 214 normalReplacer = Some("setplru"), 215 superNWays = 16, 216 normalAsVictim = true, 217 outReplace = false, 218 partialStaticPMP = true, 219 outsideRecvFlush = true, 220 saveLevel = true 221 ), 222 pftlbParameters: TLBParameters = TLBParameters( 223 name = "pftlb", 224 normalNSets = 64, 225 normalNWays = 1, 226 normalAssociative = "sa", 227 normalReplacer = Some("setplru"), 228 superNWays = 16, 229 normalAsVictim = true, 230 outReplace = false, 231 partialStaticPMP = true, 232 outsideRecvFlush = true, 233 saveLevel = true 234 ), 235 refillBothTlb: Boolean = false, 236 btlbParameters: TLBParameters = TLBParameters( 237 name = "btlb", 238 normalNSets = 1, 239 normalNWays = 64, 240 superNWays = 4, 241 ), 242 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 243 NumPerfCounters: Int = 16, 244 icacheParameters: ICacheParameters = ICacheParameters( 245 tagECC = Some("parity"), 246 dataECC = Some("parity"), 247 replacer = Some("setplru"), 248 nMissEntries = 2, 249 nProbeEntries = 2, 250 nPrefetchEntries = 2, 251 hasPrefetch = true, 252 ), 253 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 254 tagECC = Some("secded"), 255 dataECC = Some("secded"), 256 replacer = Some("setplru"), 257 nMissEntries = 16, 258 nProbeEntries = 8, 259 nReleaseEntries = 18 260 )), 261 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 262 name = "l2", 263 level = 2, 264 ways = 8, 265 sets = 1024, // default 512KB L2 266 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 267 )), 268 L2NBanks: Int = 1, 269 usePTWRepeater: Boolean = false, 270 softTLB: Boolean = false, // dpi-c l1tlb debug only 271 softPTW: Boolean = false, // dpi-c l2tlb debug only 272 softPTWDelay: Int = 1 273){ 274 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 275 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 276 277 def intSchdParams = { 278 implicit val schdType: SchedulerType = IntScheduler() 279 val pregBits = intPreg.addrWidth 280 val numRfRead = intPreg.numRead 281 val numRfWrite = intPreg.numWrite 282 SchdBlockParams(Seq( 283 IssueBlockParams(Seq( 284 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 285 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 286 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 287 IssueBlockParams(Seq( 288 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 289 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 290 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 291 IssueBlockParams(Seq( 292 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1)))), 293 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1)))), 294 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 295 IssueBlockParams(Seq( 296 ExeUnitParams(Seq(I2fCfg), Seq(VecWB(port = 6, Int.MaxValue)), Seq(Seq(IntRD(0, 0)))), 297 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 298 ), 299 numPregs = intPreg.numEntries, 300 numRfReadWrite = Some((numRfRead, numRfWrite)), 301 numDeqOutside = 0, 302 schdType = schdType, 303 rfDataWidth = intPreg.dataCfg.dataWidth, 304 numUopIn = dpParams.IntDqDeqWidth, 305 ) 306 } 307 def vfSchdParams = { 308 implicit val schdType: SchedulerType = VfScheduler() 309 val pregBits = vfPreg.addrWidth 310 val numRfRead = vfPreg.numRead 311 val numRfWrite = vfPreg.numWrite 312 SchdBlockParams(Seq( 313 IssueBlockParams(Seq( 314 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)))), 315 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 317 IssueBlockParams(Seq( 318 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)))), 319 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 320 ), 321 numPregs = vfPreg.numEntries, 322 numRfReadWrite = Some((numRfRead, numRfWrite)), 323 numDeqOutside = 0, 324 schdType = schdType, 325 rfDataWidth = vfPreg.dataCfg.dataWidth, 326 numUopIn = dpParams.FpDqDeqWidth, 327 ) 328 } 329 def memSchdParams = { 330 implicit val schdType: SchedulerType = MemScheduler() 331 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 332 val rfDataWidth = 64 333 334 SchdBlockParams(Seq( 335 IssueBlockParams(Seq( 336 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 337 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 338 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 339 IssueBlockParams(Seq( 340 ExeUnitParams(Seq(StaCfg), Seq(), Seq(Seq(IntRD(10, 0)))), 341 ExeUnitParams(Seq(StaCfg), Seq(), Seq(Seq(IntRD(11, 0)))), 342 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 343 IssueBlockParams(Seq( 344 ExeUnitParams(Seq(StdCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 345 ExeUnitParams(Seq(StdCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 346 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 347 ), 348 numPregs = intPreg.numEntries max vfPreg.numEntries, 349 numRfReadWrite = None, 350 numDeqOutside = 0, 351 schdType = schdType, 352 rfDataWidth = rfDataWidth, 353 numUopIn = dpParams.LsDqDeqWidth, 354 ) 355 } 356 357 def backendParams: BackendParams = backend.BackendParams(Map( 358 IntScheduler() -> intSchdParams, 359 VfScheduler() -> vfSchdParams, 360 MemScheduler() -> memSchdParams, 361 ), Seq( 362 intPreg, 363 vfPreg, 364 )) 365} 366 367case object DebugOptionsKey extends Field[DebugOptions] 368 369case class DebugOptions 370( 371 FPGAPlatform: Boolean = false, 372 EnableDifftest: Boolean = false, 373 AlwaysBasicDiff: Boolean = true, 374 EnableDebug: Boolean = false, 375 EnablePerfDebug: Boolean = true, 376 UseDRAMSim: Boolean = false, 377 EnableTopDown: Boolean = false 378) 379 380trait HasXSParameter { 381 382 implicit val p: Parameters 383 384 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 385 386 val coreParams = p(XSCoreParamsKey) 387 val env = p(DebugOptionsKey) 388 389 val XLEN = coreParams.XLEN 390 val VLEN = coreParams.VLEN 391 val minFLen = 32 392 val fLen = 64 393 def xLen = XLEN 394 395 val HasMExtension = coreParams.HasMExtension 396 val HasCExtension = coreParams.HasCExtension 397 val HasDiv = coreParams.HasDiv 398 val HasIcache = coreParams.HasICache 399 val HasDcache = coreParams.HasDCache 400 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 401 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 402 val AsidLength = coreParams.AsidLength 403 val ReSelectLen = coreParams.ReSelectLen 404 val AddrBytes = AddrBits / 8 // unused 405 val DataBits = XLEN 406 val DataBytes = DataBits / 8 407 val HasFPU = coreParams.HasFPU 408 val HasVPU = coreParams.HasVPU 409 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 410 val FetchWidth = coreParams.FetchWidth 411 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 412 val EnableBPU = coreParams.EnableBPU 413 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 414 val EnableRAS = coreParams.EnableRAS 415 val EnableLB = coreParams.EnableLB 416 val EnableLoop = coreParams.EnableLoop 417 val EnableSC = coreParams.EnableSC 418 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 419 val HistoryLength = coreParams.HistoryLength 420 val EnableGHistDiff = coreParams.EnableGHistDiff 421 val UbtbGHRLength = coreParams.UbtbGHRLength 422 val UbtbSize = coreParams.UbtbSize 423 val EnableFauFTB = coreParams.EnableFauFTB 424 val FtbSize = coreParams.FtbSize 425 val FtbWays = coreParams.FtbWays 426 val RasSize = coreParams.RasSize 427 428 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 429 coreParams.branchPredictor(resp_in, p) 430 } 431 val numBr = coreParams.numBr 432 val TageTableInfos = coreParams.TageTableInfos 433 val TageBanks = coreParams.numBr 434 val SCNRows = coreParams.SCNRows 435 val SCCtrBits = coreParams.SCCtrBits 436 val SCHistLens = coreParams.SCHistLens 437 val SCNTables = coreParams.SCNTables 438 439 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 440 case ((n, cb), h) => (n, cb, h) 441 } 442 val ITTageTableInfos = coreParams.ITTageTableInfos 443 type FoldedHistoryInfo = Tuple2[Int, Int] 444 val foldedGHistInfos = 445 (TageTableInfos.map{ case (nRows, h, t) => 446 if (h > 0) 447 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 448 else 449 Set[FoldedHistoryInfo]() 450 }.reduce(_++_).toSet ++ 451 SCTableInfos.map{ case (nRows, _, h) => 452 if (h > 0) 453 Set((h, min(log2Ceil(nRows/TageBanks), h))) 454 else 455 Set[FoldedHistoryInfo]() 456 }.reduce(_++_).toSet ++ 457 ITTageTableInfos.map{ case (nRows, h, t) => 458 if (h > 0) 459 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 460 else 461 Set[FoldedHistoryInfo]() 462 }.reduce(_++_) ++ 463 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 464 ).toList 465 466 467 468 val CacheLineSize = coreParams.CacheLineSize 469 val CacheLineHalfWord = CacheLineSize / 16 470 val ExtHistoryLength = HistoryLength + 64 471 val IBufSize = coreParams.IBufSize 472 val DecodeWidth = coreParams.DecodeWidth 473 val RenameWidth = coreParams.RenameWidth 474 val CommitWidth = coreParams.CommitWidth 475 val FtqSize = coreParams.FtqSize 476 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 477 val NRPhyRegs = coreParams.NRPhyRegs 478 val PhyRegIdxWidth = log2Up(NRPhyRegs) 479 val IntPhyRegs = coreParams.IntPhyRegs 480 val VfPhyRegs = coreParams.VfPhyRegs 481 val IntPregIdxWidth = log2Up(IntPhyRegs) 482 val VfPregIdxWidth = log2Up(VfPhyRegs) 483 val RobSize = coreParams.RobSize 484 val IntRefCounterWidth = log2Ceil(RobSize) 485 val LoadQueueSize = coreParams.LoadQueueSize 486 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 487 val StoreQueueSize = coreParams.StoreQueueSize 488 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 489 val VlsQueueSize = coreParams.VlsQueueSize 490 val dpParams = coreParams.dpParams 491 492 def backendParams: BackendParams = coreParams.backendParams 493 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 494 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 495 val LoadPipelineWidth = coreParams.LoadPipelineWidth 496 val StorePipelineWidth = coreParams.StorePipelineWidth 497 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 498 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 499 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 500 val StoreBufferSize = coreParams.StoreBufferSize 501 val StoreBufferThreshold = coreParams.StoreBufferThreshold 502 val EnsbufferWidth = coreParams.EnsbufferWidth 503 val UncacheBufferSize = coreParams.UncacheBufferSize 504 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 505 val EnableFastForward = coreParams.EnableFastForward 506 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 507 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 508 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 509 val EnableDCacheWPU = coreParams.EnableDCacheWPU 510 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 511 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 512 val asidLen = coreParams.MMUAsidLen 513 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 514 val refillBothTlb = coreParams.refillBothTlb 515 val itlbParams = coreParams.itlbParameters 516 val ldtlbParams = coreParams.ldtlbParameters 517 val sttlbParams = coreParams.sttlbParameters 518 val pftlbParams = coreParams.pftlbParameters 519 val btlbParams = coreParams.btlbParameters 520 val l2tlbParams = coreParams.l2tlbParameters 521 val NumPerfCounters = coreParams.NumPerfCounters 522 523 val instBytes = if (HasCExtension) 2 else 4 524 val instOffsetBits = log2Ceil(instBytes) 525 526 val icacheParameters = coreParams.icacheParameters 527 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 528 529 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 530 // for constrained LR/SC loop 531 val LRSCCycles = 64 532 // for lr storm 533 val LRSCBackOff = 8 534 535 // cache hierarchy configurations 536 val l1BusDataWidth = 256 537 538 // load violation predict 539 val ResetTimeMax2Pow = 20 //1078576 540 val ResetTimeMin2Pow = 10 //1024 541 // wait table parameters 542 val WaitTableSize = 1024 543 val MemPredPCWidth = log2Up(WaitTableSize) 544 val LWTUse2BitCounter = true 545 // store set parameters 546 val SSITSize = WaitTableSize 547 val LFSTSize = 32 548 val SSIDWidth = log2Up(LFSTSize) 549 val LFSTWidth = 4 550 val StoreSetEnable = true // LWT will be disabled if SS is enabled 551 552 val PCntIncrStep: Int = 6 553 val numPCntHc: Int = 25 554 val numPCntPtw: Int = 19 555 556 val numCSRPCntFrontend = 8 557 val numCSRPCntCtrl = 8 558 val numCSRPCntLsu = 8 559 val numCSRPCntHc = 5 560} 561