1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableFauFTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 val ftb = Module(new FTB()(p)) 101 val ubtb =Module(new FauFTB()(p)) 102 // val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 val preds = Seq(ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 ubtb.io.in.bits.resp_in(0) := resp_in 115 tage.io.in.bits.resp_in(0) := ubtb.io.out 116 ftb.io.in.bits.resp_in(0) := tage.io.out 117 ittage.io.in.bits.resp_in(0) := ftb.io.out 118 ras.io.in.bits.resp_in(0) := ittage.io.out 119 120 (preds, ras.io.out) 121 }), 122 IBufSize: Int = 48, 123 DecodeWidth: Int = 6, 124 RenameWidth: Int = 6, 125 CommitWidth: Int = 6, 126 FtqSize: Int = 64, 127 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 128 IssQueSize: Int = 16, 129 NRPhyRegs: Int = 192, 130 LoadQueueSize: Int = 80, 131 LoadQueueNWriteBanks: Int = 8, 132 StoreQueueSize: Int = 64, 133 StoreQueueNWriteBanks: Int = 8, 134 RobSize: Int = 256, 135 dpParams: DispatchParameters = DispatchParameters( 136 IntDqSize = 16, 137 FpDqSize = 16, 138 LsDqSize = 16, 139 IntDqDeqWidth = 4, 140 FpDqDeqWidth = 4, 141 LsDqDeqWidth = 4 142 ), 143 exuParameters: ExuParameters = ExuParameters( 144 JmpCnt = 1, 145 AluCnt = 4, 146 MulCnt = 0, 147 MduCnt = 2, 148 FmacCnt = 4, 149 FmiscCnt = 2, 150 FmiscDivSqrtCnt = 0, 151 LduCnt = 2, 152 StuCnt = 2 153 ), 154 LoadPipelineWidth: Int = 2, 155 StorePipelineWidth: Int = 2, 156 StoreBufferSize: Int = 16, 157 StoreBufferThreshold: Int = 7, 158 EnsbufferWidth: Int = 2, 159 EnableLoadToLoadForward: Boolean = true, 160 EnableFastForward: Boolean = false, 161 EnableLdVioCheckAfterReset: Boolean = true, 162 EnableSoftPrefetchAfterReset: Boolean = true, 163 EnableCacheErrorAfterReset: Boolean = true, 164 EnableAccurateLoadError: Boolean = true, 165 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 166 itlbParameters: TLBParameters = TLBParameters( 167 name = "itlb", 168 fetchi = true, 169 useDmode = false, 170 normalNWays = 32, 171 normalReplacer = Some("plru"), 172 superNWays = 4, 173 superReplacer = Some("plru") 174 ), 175 ldtlbParameters: TLBParameters = TLBParameters( 176 name = "ldtlb", 177 normalNSets = 64, 178 normalNWays = 1, 179 normalAssociative = "sa", 180 normalReplacer = Some("setplru"), 181 superNWays = 16, 182 normalAsVictim = true, 183 outReplace = false, 184 partialStaticPMP = true, 185 outsideRecvFlush = true, 186 saveLevel = true 187 ), 188 sttlbParameters: TLBParameters = TLBParameters( 189 name = "sttlb", 190 normalNSets = 64, 191 normalNWays = 1, 192 normalAssociative = "sa", 193 normalReplacer = Some("setplru"), 194 superNWays = 16, 195 normalAsVictim = true, 196 outReplace = false, 197 partialStaticPMP = true, 198 outsideRecvFlush = true, 199 saveLevel = true 200 ), 201 refillBothTlb: Boolean = false, 202 btlbParameters: TLBParameters = TLBParameters( 203 name = "btlb", 204 normalNSets = 1, 205 normalNWays = 64, 206 superNWays = 4, 207 ), 208 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 209 NumPerfCounters: Int = 16, 210 icacheParameters: ICacheParameters = ICacheParameters( 211 tagECC = Some("parity"), 212 dataECC = Some("parity"), 213 replacer = Some("setplru"), 214 nMissEntries = 2, 215 nProbeEntries = 2, 216 nPrefetchEntries = 2, 217 hasPrefetch = true, 218 ), 219 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 220 tagECC = Some("secded"), 221 dataECC = Some("secded"), 222 replacer = Some("setplru"), 223 nMissEntries = 16, 224 nProbeEntries = 8, 225 nReleaseEntries = 18 226 )), 227 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 228 name = "l2", 229 level = 2, 230 ways = 8, 231 sets = 1024, // default 512KB L2 232 prefetch = Some(huancun.prefetch.BOPParameters()) 233 )), 234 L2NBanks: Int = 1, 235 usePTWRepeater: Boolean = false, 236 softPTW: Boolean = false // dpi-c debug only 237){ 238 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 239 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 240 241 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 242 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 243 244 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 245 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 246 247 val fpExuConfigs = 248 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 249 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 250 251 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 252} 253 254case object DebugOptionsKey extends Field[DebugOptions] 255 256case class DebugOptions 257( 258 FPGAPlatform: Boolean = false, 259 EnableDifftest: Boolean = false, 260 AlwaysBasicDiff: Boolean = true, 261 EnableDebug: Boolean = false, 262 EnablePerfDebug: Boolean = true, 263 UseDRAMSim: Boolean = false, 264 EnableTopDown: Boolean = false 265) 266 267trait HasXSParameter { 268 269 implicit val p: Parameters 270 271 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 272 273 val coreParams = p(XSCoreParamsKey) 274 val env = p(DebugOptionsKey) 275 276 val XLEN = coreParams.XLEN 277 val minFLen = 32 278 val fLen = 64 279 def xLen = XLEN 280 281 val HasMExtension = coreParams.HasMExtension 282 val HasCExtension = coreParams.HasCExtension 283 val HasDiv = coreParams.HasDiv 284 val HasIcache = coreParams.HasICache 285 val HasDcache = coreParams.HasDCache 286 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 287 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 288 val AsidLength = coreParams.AsidLength 289 val AddrBytes = AddrBits / 8 // unused 290 val DataBits = XLEN 291 val DataBytes = DataBits / 8 292 val HasFPU = coreParams.HasFPU 293 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 294 val FetchWidth = coreParams.FetchWidth 295 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 296 val EnableBPU = coreParams.EnableBPU 297 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 298 val EnableRAS = coreParams.EnableRAS 299 val EnableLB = coreParams.EnableLB 300 val EnableLoop = coreParams.EnableLoop 301 val EnableSC = coreParams.EnableSC 302 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 303 val HistoryLength = coreParams.HistoryLength 304 val EnableGHistDiff = coreParams.EnableGHistDiff 305 val UbtbGHRLength = coreParams.UbtbGHRLength 306 val UbtbSize = coreParams.UbtbSize 307 val EnableFauFTB = coreParams.EnableFauFTB 308 val FtbSize = coreParams.FtbSize 309 val FtbWays = coreParams.FtbWays 310 val RasSize = coreParams.RasSize 311 312 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 313 coreParams.branchPredictor(resp_in, p) 314 } 315 val numBr = coreParams.numBr 316 val TageTableInfos = coreParams.TageTableInfos 317 val TageBanks = coreParams.numBr 318 val SCNRows = coreParams.SCNRows 319 val SCCtrBits = coreParams.SCCtrBits 320 val SCHistLens = coreParams.SCHistLens 321 val SCNTables = coreParams.SCNTables 322 323 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 324 case ((n, cb), h) => (n, cb, h) 325 } 326 val ITTageTableInfos = coreParams.ITTageTableInfos 327 type FoldedHistoryInfo = Tuple2[Int, Int] 328 val foldedGHistInfos = 329 (TageTableInfos.map{ case (nRows, h, t) => 330 if (h > 0) 331 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 332 else 333 Set[FoldedHistoryInfo]() 334 }.reduce(_++_).toSet ++ 335 SCTableInfos.map{ case (nRows, _, h) => 336 if (h > 0) 337 Set((h, min(log2Ceil(nRows/TageBanks), h))) 338 else 339 Set[FoldedHistoryInfo]() 340 }.reduce(_++_).toSet ++ 341 ITTageTableInfos.map{ case (nRows, h, t) => 342 if (h > 0) 343 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 344 else 345 Set[FoldedHistoryInfo]() 346 }.reduce(_++_) ++ 347 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 348 ).toList 349 350 351 352 val CacheLineSize = coreParams.CacheLineSize 353 val CacheLineHalfWord = CacheLineSize / 16 354 val ExtHistoryLength = HistoryLength + 64 355 val IBufSize = coreParams.IBufSize 356 val DecodeWidth = coreParams.DecodeWidth 357 val RenameWidth = coreParams.RenameWidth 358 val CommitWidth = coreParams.CommitWidth 359 val FtqSize = coreParams.FtqSize 360 val IssQueSize = coreParams.IssQueSize 361 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 362 val NRPhyRegs = coreParams.NRPhyRegs 363 val PhyRegIdxWidth = log2Up(NRPhyRegs) 364 val RobSize = coreParams.RobSize 365 val IntRefCounterWidth = log2Ceil(RobSize) 366 val LoadQueueSize = coreParams.LoadQueueSize 367 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 368 val StoreQueueSize = coreParams.StoreQueueSize 369 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 370 val dpParams = coreParams.dpParams 371 val exuParameters = coreParams.exuParameters 372 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 373 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 374 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 375 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 376 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 377 val LoadPipelineWidth = coreParams.LoadPipelineWidth 378 val StorePipelineWidth = coreParams.StorePipelineWidth 379 val StoreBufferSize = coreParams.StoreBufferSize 380 val StoreBufferThreshold = coreParams.StoreBufferThreshold 381 val EnsbufferWidth = coreParams.EnsbufferWidth 382 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 383 val EnableFastForward = coreParams.EnableFastForward 384 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 385 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 386 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 387 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 388 val asidLen = coreParams.MMUAsidLen 389 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 390 val refillBothTlb = coreParams.refillBothTlb 391 val itlbParams = coreParams.itlbParameters 392 val ldtlbParams = coreParams.ldtlbParameters 393 val sttlbParams = coreParams.sttlbParameters 394 val btlbParams = coreParams.btlbParameters 395 val l2tlbParams = coreParams.l2tlbParameters 396 val NumPerfCounters = coreParams.NumPerfCounters 397 398 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 399 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 400 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 401 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 402 403 val instBytes = if (HasCExtension) 2 else 4 404 val instOffsetBits = log2Ceil(instBytes) 405 406 val icacheParameters = coreParams.icacheParameters 407 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 408 409 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 410 // for constrained LR/SC loop 411 val LRSCCycles = 64 412 // for lr storm 413 val LRSCBackOff = 8 414 415 // cache hierarchy configurations 416 val l1BusDataWidth = 256 417 418 // load violation predict 419 val ResetTimeMax2Pow = 20 //1078576 420 val ResetTimeMin2Pow = 10 //1024 421 // wait table parameters 422 val WaitTableSize = 1024 423 val MemPredPCWidth = log2Up(WaitTableSize) 424 val LWTUse2BitCounter = true 425 // store set parameters 426 val SSITSize = WaitTableSize 427 val LFSTSize = 32 428 val SSIDWidth = log2Up(LFSTSize) 429 val LFSTWidth = 4 430 val StoreSetEnable = true // LWT will be disabled if SS is enabled 431 432 val loadExuConfigs = coreParams.loadExuConfigs 433 val storeExuConfigs = coreParams.storeExuConfigs 434 435 val intExuConfigs = coreParams.intExuConfigs 436 437 val fpExuConfigs = coreParams.fpExuConfigs 438 439 val exuConfigs = coreParams.exuConfigs 440 441 val PCntIncrStep: Int = 6 442 val numPCntHc: Int = 25 443 val numPCntPtw: Int = 19 444 445 val numCSRPCntFrontend = 8 446 val numCSRPCntCtrl = 8 447 val numCSRPCntLsu = 8 448 val numCSRPCntHc = 5 449} 450