1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import xiangshan.ExceptionNO._ 20import xiangshan.backend.fu._ 21import xiangshan.backend.fu.fpu._ 22import xiangshan.backend.fu.vector._ 23import xiangshan.backend.issue._ 24import xiangshan.backend.fu.FuConfig 25 26package object xiangshan { 27 object SrcType { 28 def imm = "b000".U 29 def pc = "b000".U 30 def xp = "b001".U 31 def fp = "b010".U 32 def vp = "b100".U 33 34 // alias 35 def reg = this.xp 36 def DC = imm // Don't Care 37 def X = BitPat("b000") 38 39 def isPc(srcType: UInt) = srcType===pc 40 def isImm(srcType: UInt) = srcType===imm 41 def isReg(srcType: UInt) = srcType(0) 42 def isXp(srcType: UInt) = srcType(0) 43 def isFp(srcType: UInt) = srcType(1) 44 def isVp(srcType: UInt) = srcType(2) 45 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 46 def isNotReg(srcType: UInt): Bool = !srcType.orR 47 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 48 def apply() = UInt(3.W) 49 } 50 51 object SrcState { 52 def busy = "b0".U 53 def rdy = "b1".U 54 // def specRdy = "b10".U // speculative ready, for future use 55 def apply() = UInt(1.W) 56 57 def isReady(state: UInt): Bool = state === this.rdy 58 def isBusy(state: UInt): Bool = state === this.busy 59 } 60 61 def FuOpTypeWidth = 8 62 object FuOpType { 63 def apply() = UInt(FuOpTypeWidth.W) 64 def X = BitPat("b00000000") 65 } 66 67 object VlduType { 68 def dummy = 0.U 69 } 70 71 object VstuType { 72 def dummy = 0.U 73 } 74 75 object CommitType { 76 def NORMAL = "b000".U // int/fp 77 def BRANCH = "b001".U // branch 78 def LOAD = "b010".U // load 79 def STORE = "b011".U // store 80 81 def apply() = UInt(3.W) 82 def isFused(commitType: UInt): Bool = commitType(2) 83 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 84 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 85 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 86 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 87 } 88 89 object RedirectLevel { 90 def flushAfter = "b0".U 91 def flush = "b1".U 92 93 def apply() = UInt(1.W) 94 // def isUnconditional(level: UInt) = level(1) 95 def flushItself(level: UInt) = level(0) 96 // def isException(level: UInt) = level(1) && level(0) 97 } 98 99 object ExceptionVec { 100 def apply() = Vec(16, Bool()) 101 } 102 103 object PMAMode { 104 def R = "b1".U << 0 //readable 105 def W = "b1".U << 1 //writeable 106 def X = "b1".U << 2 //executable 107 def I = "b1".U << 3 //cacheable: icache 108 def D = "b1".U << 4 //cacheable: dcache 109 def S = "b1".U << 5 //enable speculative access 110 def A = "b1".U << 6 //enable atomic operation, A imply R & W 111 def C = "b1".U << 7 //if it is cacheable is configable 112 def Reserved = "b0".U 113 114 def apply() = UInt(7.W) 115 116 def read(mode: UInt) = mode(0) 117 def write(mode: UInt) = mode(1) 118 def execute(mode: UInt) = mode(2) 119 def icache(mode: UInt) = mode(3) 120 def dcache(mode: UInt) = mode(4) 121 def speculate(mode: UInt) = mode(5) 122 def atomic(mode: UInt) = mode(6) 123 def configable_cache(mode: UInt) = mode(7) 124 125 def strToMode(s: String) = { 126 var result = 0.U(8.W) 127 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 128 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 129 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 130 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 131 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 132 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 133 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 134 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 135 result 136 } 137 } 138 139 140 object CSROpType { 141 def jmp = "b000".U 142 def wrt = "b001".U 143 def set = "b010".U 144 def clr = "b011".U 145 def wfi = "b100".U 146 def wrti = "b101".U 147 def seti = "b110".U 148 def clri = "b111".U 149 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 150 } 151 152 // jump 153 object JumpOpType { 154 def jal = "b00".U 155 def jalr = "b01".U 156 def auipc = "b10".U 157// def call = "b11_011".U 158// def ret = "b11_100".U 159 def jumpOpisJalr(op: UInt) = op(0) 160 def jumpOpisAuipc(op: UInt) = op(1) 161 } 162 163 object FenceOpType { 164 def fence = "b10000".U 165 def sfence = "b10001".U 166 def fencei = "b10010".U 167 def nofence= "b00000".U 168 } 169 170 object ALUOpType { 171 // shift optype 172 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 173 def sll = "b000_0001".U // sll: src1 << src2 174 175 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 176 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 177 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 178 179 def srl = "b000_0101".U // srl: src1 >> src2 180 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 181 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 182 183 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 184 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 185 186 // RV64 32bit optype 187 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 188 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 189 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 190 191 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 192 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 193 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 194 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 195 196 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 197 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 198 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 199 def rolw = "b001_1100".U 200 def rorw = "b001_1101".U 201 202 // ADD-op 203 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 204 def add = "b010_0001".U // add: src1 + src2 205 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 206 207 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 208 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 209 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 210 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 211 212 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 213 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 214 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 215 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 216 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 217 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 218 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 219 220 // SUB-op: src1 - src2 221 def sub = "b011_0000".U 222 def sltu = "b011_0001".U 223 def slt = "b011_0010".U 224 def maxu = "b011_0100".U 225 def minu = "b011_0101".U 226 def max = "b011_0110".U 227 def min = "b011_0111".U 228 229 // branch 230 def beq = "b111_0000".U 231 def bne = "b111_0010".U 232 def blt = "b111_1000".U 233 def bge = "b111_1010".U 234 def bltu = "b111_1100".U 235 def bgeu = "b111_1110".U 236 237 // misc optype 238 def and = "b100_0000".U 239 def andn = "b100_0001".U 240 def or = "b100_0010".U 241 def orn = "b100_0011".U 242 def xor = "b100_0100".U 243 def xnor = "b100_0101".U 244 def orcb = "b100_0110".U 245 246 def sextb = "b100_1000".U 247 def packh = "b100_1001".U 248 def sexth = "b100_1010".U 249 def packw = "b100_1011".U 250 251 def revb = "b101_0000".U 252 def rev8 = "b101_0001".U 253 def pack = "b101_0010".U 254 def orh48 = "b101_0011".U 255 256 def szewl1 = "b101_1000".U 257 def szewl2 = "b101_1001".U 258 def szewl3 = "b101_1010".U 259 def byte2 = "b101_1011".U 260 261 def andlsb = "b110_0000".U 262 def andzexth = "b110_0001".U 263 def orlsb = "b110_0010".U 264 def orzexth = "b110_0011".U 265 def xorlsb = "b110_0100".U 266 def xorzexth = "b110_0101".U 267 def orcblsb = "b110_0110".U 268 def orcbzexth = "b110_0111".U 269 def vsetvli1 = "b1000_0000".U 270 def vsetvli2 = "b1000_0100".U 271 def vsetvl1 = "b1000_0001".U 272 def vsetvl2 = "b1000_0101".U 273 def vsetivli1 = "b1000_0010".U 274 def vsetivli2 = "b1000_0110".U 275 276 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 277 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 278 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 279 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 280 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 281 def isVsetvl(func: UInt) = isVset(func) && func(0) 282 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 283 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 284 285 def apply() = UInt(FuOpTypeWidth.W) 286 } 287 288 object BRUOpType { 289 // branch 290 def beq = "b000_000".U 291 def bne = "b000_001".U 292 def blt = "b000_100".U 293 def bge = "b000_101".U 294 def bltu = "b001_000".U 295 def bgeu = "b001_001".U 296 297 def getBranchType(func: UInt) = func(3, 1) 298 def isBranchInvert(func: UInt) = func(0) 299 } 300 301 object MULOpType { 302 // mul 303 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 304 def mul = "b00000".U 305 def mulh = "b00001".U 306 def mulhsu = "b00010".U 307 def mulhu = "b00011".U 308 def mulw = "b00100".U 309 310 def mulw7 = "b01100".U 311 def isSign(op: UInt) = !op(1) 312 def isW(op: UInt) = op(2) 313 def isH(op: UInt) = op(1, 0) =/= 0.U 314 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 315 } 316 317 object DIVOpType { 318 // div 319 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 320 def div = "b10000".U 321 def divu = "b10010".U 322 def rem = "b10001".U 323 def remu = "b10011".U 324 325 def divw = "b10100".U 326 def divuw = "b10110".U 327 def remw = "b10101".U 328 def remuw = "b10111".U 329 330 def isSign(op: UInt) = !op(1) 331 def isW(op: UInt) = op(2) 332 def isH(op: UInt) = op(0) 333 } 334 335 object MDUOpType { 336 // mul 337 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 338 def mul = "b00000".U 339 def mulh = "b00001".U 340 def mulhsu = "b00010".U 341 def mulhu = "b00011".U 342 def mulw = "b00100".U 343 344 def mulw7 = "b01100".U 345 346 // div 347 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 348 def div = "b10000".U 349 def divu = "b10010".U 350 def rem = "b10001".U 351 def remu = "b10011".U 352 353 def divw = "b10100".U 354 def divuw = "b10110".U 355 def remw = "b10101".U 356 def remuw = "b10111".U 357 358 def isMul(op: UInt) = !op(4) 359 def isDiv(op: UInt) = op(4) 360 361 def isDivSign(op: UInt) = isDiv(op) && !op(1) 362 def isW(op: UInt) = op(2) 363 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 364 def getMulOp(op: UInt) = op(1, 0) 365 } 366 367 object LSUOpType { 368 // load pipeline 369 370 // normal load 371 // Note: bit(1, 0) are size, DO NOT CHANGE 372 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 373 def lb = "b0000".U 374 def lh = "b0001".U 375 def lw = "b0010".U 376 def ld = "b0011".U 377 def lbu = "b0100".U 378 def lhu = "b0101".U 379 def lwu = "b0110".U 380 381 // Zicbop software prefetch 382 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 383 def prefetch_i = "b1000".U // TODO 384 def prefetch_r = "b1001".U 385 def prefetch_w = "b1010".U 386 387 def isPrefetch(op: UInt): Bool = op(3) 388 389 // store pipeline 390 // normal store 391 // bit encoding: | store 00 | size(2bit) | 392 def sb = "b0000".U 393 def sh = "b0001".U 394 def sw = "b0010".U 395 def sd = "b0011".U 396 397 // l1 cache op 398 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 399 def cbo_zero = "b0111".U 400 401 // llc op 402 // bit encoding: | prefetch 11 | suboptype(2bit) | 403 def cbo_clean = "b1100".U 404 def cbo_flush = "b1101".U 405 def cbo_inval = "b1110".U 406 407 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 408 409 // atomics 410 // bit(1, 0) are size 411 // since atomics use a different fu type 412 // so we can safely reuse other load/store's encodings 413 // bit encoding: | optype(4bit) | size (2bit) | 414 def lr_w = "b000010".U 415 def sc_w = "b000110".U 416 def amoswap_w = "b001010".U 417 def amoadd_w = "b001110".U 418 def amoxor_w = "b010010".U 419 def amoand_w = "b010110".U 420 def amoor_w = "b011010".U 421 def amomin_w = "b011110".U 422 def amomax_w = "b100010".U 423 def amominu_w = "b100110".U 424 def amomaxu_w = "b101010".U 425 426 def lr_d = "b000011".U 427 def sc_d = "b000111".U 428 def amoswap_d = "b001011".U 429 def amoadd_d = "b001111".U 430 def amoxor_d = "b010011".U 431 def amoand_d = "b010111".U 432 def amoor_d = "b011011".U 433 def amomin_d = "b011111".U 434 def amomax_d = "b100011".U 435 def amominu_d = "b100111".U 436 def amomaxu_d = "b101011".U 437 438 def size(op: UInt) = op(1,0) 439 } 440 441 object BKUOpType { 442 443 def clmul = "b000000".U 444 def clmulh = "b000001".U 445 def clmulr = "b000010".U 446 def xpermn = "b000100".U 447 def xpermb = "b000101".U 448 449 def clz = "b001000".U 450 def clzw = "b001001".U 451 def ctz = "b001010".U 452 def ctzw = "b001011".U 453 def cpop = "b001100".U 454 def cpopw = "b001101".U 455 456 // 01xxxx is reserve 457 def aes64es = "b100000".U 458 def aes64esm = "b100001".U 459 def aes64ds = "b100010".U 460 def aes64dsm = "b100011".U 461 def aes64im = "b100100".U 462 def aes64ks1i = "b100101".U 463 def aes64ks2 = "b100110".U 464 465 // merge to two instruction sm4ks & sm4ed 466 def sm4ed0 = "b101000".U 467 def sm4ed1 = "b101001".U 468 def sm4ed2 = "b101010".U 469 def sm4ed3 = "b101011".U 470 def sm4ks0 = "b101100".U 471 def sm4ks1 = "b101101".U 472 def sm4ks2 = "b101110".U 473 def sm4ks3 = "b101111".U 474 475 def sha256sum0 = "b110000".U 476 def sha256sum1 = "b110001".U 477 def sha256sig0 = "b110010".U 478 def sha256sig1 = "b110011".U 479 def sha512sum0 = "b110100".U 480 def sha512sum1 = "b110101".U 481 def sha512sig0 = "b110110".U 482 def sha512sig1 = "b110111".U 483 484 def sm3p0 = "b111000".U 485 def sm3p1 = "b111001".U 486 } 487 488 object BTBtype { 489 def B = "b00".U // branch 490 def J = "b01".U // jump 491 def I = "b10".U // indirect 492 def R = "b11".U // return 493 494 def apply() = UInt(2.W) 495 } 496 497 object SelImm { 498 def IMM_X = "b0111".U 499 def IMM_S = "b0000".U 500 def IMM_SB = "b0001".U 501 def IMM_U = "b0010".U 502 def IMM_UJ = "b0011".U 503 def IMM_I = "b0100".U 504 def IMM_Z = "b0101".U 505 def INVALID_INSTR = "b0110".U 506 def IMM_B6 = "b1000".U 507 508 def IMM_OPIVIS = "b1001".U 509 def IMM_OPIVIU = "b1010".U 510 def IMM_VSETVLI = "b1100".U 511 def IMM_VSETIVLI = "b1101".U 512 513 def X = BitPat("b0000") 514 515 def apply() = UInt(4.W) 516 } 517 518 object ExceptionNO { 519 def instrAddrMisaligned = 0 520 def instrAccessFault = 1 521 def illegalInstr = 2 522 def breakPoint = 3 523 def loadAddrMisaligned = 4 524 def loadAccessFault = 5 525 def storeAddrMisaligned = 6 526 def storeAccessFault = 7 527 def ecallU = 8 528 def ecallS = 9 529 def ecallM = 11 530 def instrPageFault = 12 531 def loadPageFault = 13 532 // def singleStep = 14 533 def storePageFault = 15 534 def priorities = Seq( 535 breakPoint, // TODO: different BP has different priority 536 instrPageFault, 537 instrAccessFault, 538 illegalInstr, 539 instrAddrMisaligned, 540 ecallM, ecallS, ecallU, 541 storeAddrMisaligned, 542 loadAddrMisaligned, 543 storePageFault, 544 loadPageFault, 545 storeAccessFault, 546 loadAccessFault 547 ) 548 def all = priorities.distinct.sorted 549 def frontendSet = Seq( 550 instrAddrMisaligned, 551 instrAccessFault, 552 illegalInstr, 553 instrPageFault 554 ) 555 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 556 val new_vec = Wire(ExceptionVec()) 557 new_vec.foreach(_ := false.B) 558 select.foreach(i => new_vec(i) := vec(i)) 559 new_vec 560 } 561 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 562 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 563 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 564 partialSelect(vec, fuConfig.exceptionOut) 565 } 566} 567